Quoting Patrick Georgi patrick@georgi-clan.de:
Am 30.07.2010 19:35, schrieb austinro@msu.edu:
I have a Jetway 7F4K1G5S-LF board I'm trying to get working.
Just to make things clear - that's a Via C7 board, yes?
Yes.
Any ideas?
We moved the C7 boards over to CAR (cache as RAM), but couldn't test all of them (due to availability etc). Disabling cache before RAM is available (and all data structures, esp. the stack are moved to RAM) makes the system hang.
From looking at the board's romstage.c, it seems that early_mtrr_init is ran before RAM init, but after CAR enable.
Do you get further after disabling early_mtrr_init (which disables caching to activate the new MTRR config) completely?
Commenting out the call to early_mtrr_init() lets coreboot run to completion.
That's odd. I assumed the call to "write_cr0(cr0)" in cache.h was responsible somehow, since that was where it stopped when "early_mtrr_init" called "disable_cache", but I left the print statements in disable_cache, and they were all printed repeatedly this time, so "write_cr0" only causes a problem when called early (during "early_mtrr_init")?
...
Tried it again and with memtest as the payload and it doesn't see any memory. Memtest pops up on the screen : L1 cache: 64K L2 cache: 128K L3 cache: none Memory : 0K (That last one is a zero K).
Hmmm.
(Thanks Patrick!)