* Uwe Hermann uwe@hermann-uwe.de [070527 22:45]:
Other entries on the 440BX TODO list are:
- Make RAM init generic, not hardcoded to the S1846
This patch was sent around by Alfred Wanga on april 30th
- Port all 440BX boards to Cache as RAM
Is there a working CAR implementation for 440BX?
Init for the Intel 82371EB southbridge: make all ROM/BIOS regions accessible (but not writable), so that reading/loading a payload from that area can work (for instance).
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de
Acked-by: Stefan Reinauer stepan@coresystems.de