Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2024
-gerrit
commit cc1911ac17ed1ee684ec6559a7bf9e02502c4f9b Author: Stefan Reinauer reinauer@chromium.org Date: Tue Dec 11 15:51:47 2012 -0800
Add support for ENE932 EC w/ Compal firmware
Change-Id: I19b03139e7edfee6ff3e0bcef735bb36bfadc354 Signed-off-by: Stefan Reinauer reinauer@google.com --- src/ec/Kconfig | 1 + src/ec/Makefile.inc | 2 +- src/ec/compal/Kconfig | 1 + src/ec/compal/Makefile.inc | 1 + src/ec/compal/ene932/Kconfig | 4 + src/ec/compal/ene932/Makefile.inc | 3 + src/ec/compal/ene932/acpi/ac.asl | 39 ++++ src/ec/compal/ene932/acpi/battery.asl | 158 +++++++++++++++ src/ec/compal/ene932/acpi/ec.asl | 355 ++++++++++++++++++++++++++++++++++ src/ec/compal/ene932/acpi/superio.asl | 57 ++++++ src/ec/compal/ene932/chip.h | 35 ++++ src/ec/compal/ene932/ec.c | 180 +++++++++++++++++ src/ec/compal/ene932/ec.h | 56 ++++++ 13 files changed, 891 insertions(+), 1 deletion(-)
diff --git a/src/ec/Kconfig b/src/ec/Kconfig index 935b40b..0233bd9 100644 --- a/src/ec/Kconfig +++ b/src/ec/Kconfig @@ -1,3 +1,4 @@ source src/ec/acpi/Kconfig +source src/ec/compal/Kconfig source src/ec/lenovo/Kconfig source src/ec/smsc/Kconfig diff --git a/src/ec/Makefile.inc b/src/ec/Makefile.inc index b334c1f..0ddba79 100644 --- a/src/ec/Makefile.inc +++ b/src/ec/Makefile.inc @@ -1,2 +1,2 @@ subdirs-$(CONFIG_EC_ACPI) += acpi -subdirs-y += lenovo smsc +subdirs-y += compal lenovo smsc diff --git a/src/ec/compal/Kconfig b/src/ec/compal/Kconfig new file mode 100644 index 0000000..5b7899a --- /dev/null +++ b/src/ec/compal/Kconfig @@ -0,0 +1 @@ +source src/ec/compal/ene932/Kconfig diff --git a/src/ec/compal/Makefile.inc b/src/ec/compal/Makefile.inc new file mode 100644 index 0000000..ce75ca6 --- /dev/null +++ b/src/ec/compal/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_EC_COMPAL_ENE932) += ene932 diff --git a/src/ec/compal/ene932/Kconfig b/src/ec/compal/ene932/Kconfig new file mode 100644 index 0000000..47e4b7b --- /dev/null +++ b/src/ec/compal/ene932/Kconfig @@ -0,0 +1,4 @@ +config EC_COMPAL_ENE932 + bool + help + Interface to COMPAL ENE932 Embedded Controller. diff --git a/src/ec/compal/ene932/Makefile.inc b/src/ec/compal/ene932/Makefile.inc new file mode 100644 index 0000000..fb898be --- /dev/null +++ b/src/ec/compal/ene932/Makefile.inc @@ -0,0 +1,3 @@ +ramstage-y += ec.c +smm-y += ec.c +smm-y += ../../../lib/delay.c diff --git a/src/ec/compal/ene932/acpi/ac.asl b/src/ec/compal/ene932/acpi/ac.asl new file mode 100644 index 0000000..8c85fc3 --- /dev/null +++ b/src/ec/compal/ene932/acpi/ac.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Scope (EC0) + +Device (AC) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { _SB }) + + Method (_PSR) + { + Store(ADPT, Local0) + Return(Local0) + } + + Method (_STA) + { + Return (0x0F) + } +} diff --git a/src/ec/compal/ene932/acpi/battery.asl b/src/ec/compal/ene932/acpi/battery.asl new file mode 100644 index 0000000..90d8adb --- /dev/null +++ b/src/ec/compal/ene932/acpi/battery.asl @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Scope (EC0) + +Device (BATX) +{ + Name (_HID, EISAID ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { _SB }) + + Name (PBIF, Package () { + 0x00000001, // Power Unit: mAh + 0xFFFFFFFF, // Design Capacity + 0xFFFFFFFF, // Last Full Charge Capacity + 0x00000001, // Battery Technology: Rechargeable + 0xFFFFFFFF, // Design Voltage + 0x00000003, // Design Capacity of Warning + 0xFFFFFFFF, // Design Capacity of Low + 0x00000001, // Capacity Granularity 1 + 0x00000001, // Capacity Granularity 2 + "", // Model Number + "", // Serial Number + "LION", // Battery Type + "" // OEM Information + }) + + Name (PBST, Package () { + 0x00000000, // Battery State + 0xFFFFFFFF, // Battery Present Rate + 0xFFFFFFFF, // Battery Remaining Capacity + 0xFFFFFFFF, // Battery Present Voltage + }) + Name (BTNM, Zero) // Battery number + + // Workaround for full battery status, enabled by default + Name (BFWK, One) + + // Method to enable full battery workaround + Method (BFWE) + { + Store (One, BFWK) + } + + // Method to disable full battery workaround + Method (BFWD) + { + Store (Zero, BFWK) + } + + Method (_STA, 0, Serialized) + { + If (BOL0) { + Return (0x1F) + } Else { + Return (0x0F) + } + } + + Method (_BIF, 0, Serialized) + { + // Update fields from EC + Store (BAM0, Index (PBIF, 0)) + Store (BDC0, Index (PBIF, 1)) + Store (BFC0, Index (PBIF, 2)) + Store (BDV0, Index (PBIF, 4)) + Divide(BFC0, 0x64, Local0, Local1) + Multiply(Local1, 0x0A, Local1) + Store(Local1, Index(PBIF, 5)) + Divide(BFC0, 0x64, Local0, Local1) + Multiply(Local1, 0x03, Local1) + Store (Local1, Index (PBIF, 6)) + + Store (ToString(BATD), Index (PBIF, 9)) // model + Store (ToHexString(BSN0), Index (PBIF, 10)) // serial + Store (ToString(BMFN), Index (PBIF, 12)) // venor + + Store(BDN0, BTNM) // Save the battery number + + Return (PBIF) + } + + Method (_BST, 0, Serialized) + { + // + // 0: BATTERY STATE + // + // bit 0 = discharging + // bit 1 = charging + // bit 2 = critical level + // + + // Get battery state from EC and save it for the charging workaround + Store (BST0, Local0) + Store (Local0, Index (PBST, 0)) + + // + // 1: BATTERY PRESENT RATE/CURRENT + // + + Store (BAC0, Local1) + Subtract(0xFFFF, Local1, Local1) + Store (Local1, Index (PBST, 1)) + + // + // 2: BATTERY REMAINING CAPACITY + // + Multiply(BFC0, GAU0, Local1) + Divide(Local1, 0x64, Local2, Local1) + + If (LAnd (BFWK, LAnd (ADPT, LNot (Local0)))) { + // On AC power and battery is neither charging + // nor discharging. Linux expects a full battery + // to report same capacity as last full charge. + // https://bugzilla.kernel.org/show_bug.cgi?id=12632 + Store (GAU0, Local2) + + // See if within ~3% of full + ShiftRight (Local2, 5, Local3) + If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), + LLess (Local1, Add (Local2, Local3)))) + { + Store (Local2, Local1) + } + } + Store (Local1, Index (PBST, 2)) + + // + // 3: BATTERY PRESENT VOLTAGE + // + Store (BPV0, Index (PBST, 3)) + + // Check the Battery Number + If(LNotEqual(BDN0, BTNM)) { + Notify(BATX, 0x81) + } + + Return (PBST) + } +} diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl new file mode 100644 index 0000000..cb50a21 --- /dev/null +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -0,0 +1,355 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * The mainboard must define a PNOT method to handle power + * state notifications and Notify CPU device objects to + * re-evaluate their _PPC and _CST tables. + */ + +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 1) + Name (_GPE, EC_SCI) // GPE for Runtime SCI + + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + // EC Name Space Configuration + Offset(0x00), + , 1, // Reserved ; 00h.0 + LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1 + , 6, // Reserved ; 00h.2 ~ 00h.6 + HTBN, 8, // HOTKEY_BUTTON_NUMBER ; 01h For ABO Hot Key Function + HTBT, 8, // HOTKEY_BUTTON_TYPE ; 02h For ABO Hot Key Function + LMEN, 1, // Launch Manager enable .(1=Enable ) ; 03h.0, Lauanch manage + , 7, // Reserved ; 03h.1 ~ 03h.7 + ADAP, 2, // Adaptor Type ; 04h.0 ~ 1 + // 0x00 = default(65w) + // 0x01 = 65w + // 0x02 = 90w + // 0x03 = 120w + , 6, // Reserved ; 04h.2 ~ 04h.7 + Offset(0x08), // Project Common Name space definition ; 08h - 2Ch + Offset(0x2D), + DSPM, 1, // Display Mode.(0=dGPU, 1=iGPU ) ; 2Dh.0 + Offset(0x2E), + EFP1, 4, // Turbo Off P-State ; 2Eh.3-0 + Offset(0x40), // ABO Common Name space definition ; 2F - 5Ch + Offset(0x5D), + ENIB, 16, // Ext_NameSpace_Index ; 5Dh + // Ext_NameSpace_Bank ; 5Eh + ENDD, 8, // Ext_NameSpace_Data ; 5Fh + Offset(0x60), + SMPR, 8, // SMBus protocol register ; 60h + SMST, 8, // SMBus status register ; 61h + SMAD, 8, // SMBus address register ; 62h + SMCM, 8, // SMBus command register ; 63h + SMD0, 0x100, // SMBus data regs (32) ; 64h - 83h + BCNT, 8, // SMBus Block Count ; 84h + SMAA, 24, // SMBus Alarm Address ; 85h - 87h + Offset(0x90), + BMFN, 72, // Battery Manufacture name ; 90h - 98h + BATD, 56, // Battery Device name ; 99h - 9fh + Offset(0xA1), + , 1, // Reserve ; A1h.0 + VIDO, 1, // Video Out Button (1=Pressed) ; A1h.1 + TOUP, 1, // Touch Pad Button (0=On, 1=Off) ; A1h.2 + Offset(0xA2), + ODTS, 8, // OS Shutdown Temp2 (DTS) ; A2h + Offset(0xA3), + OSTY, 3, // OSTYPE : 000- XP ; A3h.0-2 + // 001- Vista + // 010- Linux + // 011- Win7 + , 4, // Reserve ; A3h.3-6 + ADPT, 1, // AC Adapter (0=OffLine, 1=OnLine) ; A3h.7 + Offset(0xA4), + PWAK, 1, // PME Wake Enable(0=Disable, 1=Enable) ; A4h.0 + MWAK, 1, // Modem Wake Enable(0/1=Disable/Enable); A4h.1 + LWAK, 1, // LAN Wake Enable (0=Disable, 1=Enable); A4h.2 + RWAK, 1, // RTC Wake Enable(0=DIsable,1=Enable) ; A4h.3 + WWAK, 1, // WLAN wake Enable (0=Disable,1=Enable); A4h.4 + UWAK, 1, // USB WAKE(0=Disable, 1=Enable) ; A4h.5 + KWAK, 1, // Keyboard WAKE(0=Disable,1=Enable) ; A4h.6 + TWAK, 1, // TouchPad WAKE(0=Disable,1=Enable) ; A4h.7 + Offset(0xA5), + CCAC, 1, // Charge Current (1=AC OFF) ; A5h.0 + AOAC, 1, // Adapter OVP (1=AC OFF) ; A5h.1 + BLAC, 1, // Batt learning (1=AC OFF) ; A5h.2 + PSRC, 1, // Command (1=AC OFF) ; A5h.3 + BOAC, 1, // Batt OVP (1=AC OFF) ; A5h.4 + LCAC, 1, // Leak Current (1=AC OFF) ; A5h.5 + AAAC, 1, // Air Adapter (1=AC OFF) ; A5h.6 + ACAC, 1, // AC Off (1=AC OFF) ; A5h.7 + Offset(0xA6), + S3ST, 1, // System entry S3 State : A6.0 + S3RM, 1, // System resume from S3 State : A6.1 + S4ST, 1, // System entry S4 State : A6.2 + S4RM, 1, // System resume from S4 State : A6.3 + S5ST, 1, // System entry S4 State : A6.4 + S5RM, 1, // System resume from S4 State : A6.5 + , 2, // Reserve ; A6h.6-7 + Offset(0xA7), + OSTT, 8, // OS Throttling Temp ; A7h + OSST, 8, // OS Shutdown Temp ; A8h + THLT, 8, // Throttling Temp ; A9h + TCNL, 8, // Tcontrol Temp ; AAh + MODE, 1, // Mode(0=Local, 1=Remote) ; ABh.0 + , 2, // Reserve ; ABh.1-2 + INIT, 1, // INITOK(0/1=Controlled by OS/EC) ; ABh.3 + FAN1, 1, // FAN1 Active ; ABh.4 + FAN2, 1, // FAN2 Active ; ABh.5 + FANT, 1, // FAN Speed Time OK ; ABh.6 + SKNM, 1, // Skin Mode (0/1=Skin Address 90/92) ; ABh.7 + SDTM, 8, // Shutdown Thermal Temperature ; ACh + FSSN, 4, // Fan Speed Step Number ; ADh.0-3 + // 00 : Fan Off + // 01 : Fan On Speed 1 + // 10 : Fan On Speed 2 + // 11 : Fan On Speed 3 + FANU, 4, // Machine Fan's number ; ADh.4-7 + PCVL, 4, // Throttling Level ; AEh.0-3 + // 0000 : Nothing + // 0001 : Clock throttling 12.5% + // 0010 : Clock throttling 25% + // 0011 : Clock throttling 37.5% + // 0100 : Clock throttling 50% + , 2, // Reserved ; AEh.4-5 + SWTO, 1, // SW Throttling (1=Active) ; AEh.6 + TTHR, 1, // HW (THRM#) Throttling (1=Active) ; AEh.7 + TTHM, 1, // TS_THERMAL(1:Throttling for thermal) ; AFh.0 + THTL, 1, // THROTTLING(1:Ctrl H/W throtting act) ; AFh.1 + , 2, // Reserved ; AFh.2-3 + NPST, 4, // Number of P-State level ; AFh.4-7 + CTMP, 8, // Current CPU Temperature ; B0h + CTML, 8, // CPU local temperature ; B1h + SKTA, 8, // Skin Temperature A ; B2h + SKTB, 8, // GPU Temperature ; B3h + SKTC, 8, // Skin Temperature C ; B4h + , 8, // Reserved ; B5h + NTMP, 8, // North Bridge Diode Temp ; B6h + Offset(0xB7), + , 1, // Reserved ; B7h.0 + SKEY, 1, // Security key event ; B7h.1 + DIGM, 1, // Digital Mode (1=Selected) ; B7h.2 + CDLE, 1, // CD lock mode enable ; B7h.3 + , 4, // Reserved ; B7h.4-7 + , 1, // Reserved ; B8h.0 + LIDF, 1, // LID flag (1=Closed, 0=Opened) ; B8h.1 + PMEE, 1, // PME event (0=off, 1=On) ; B8h.2 + PWBE, 1, // Power button event (0=off, 1=On) ; B8h.3 + RNGE, 1, // Ring in event (0=off, 1=On) ; B8h.4 + BTWE, 1, // Bluetooth wake event (0=off, 1=On) ; B8h.5 + , 2, // Reserved ; B8h.6-7 + Offset(0xB9), + BRTS, 8, // Brightness Value ; B9h + S35M, 1, // S3.5 HotKey test mode ; BAh.0 + S35S, 1, // S3.5 function status ; BAh.1 + , 2, // Reserved ; BAh.2-3 + FFEN, 1, // IRST support bit (1= Support) ; BAh.4 + FFST, 1, // IRST status flag ; BAh.5 + , 2, // Reserved ; BAh.6-7 + WLAT, 1, // Wireless LAN (0=Inactive, 1=Active) ; BBh.0 + BTAT, 1, // BlueTooth (0=Inactive, 1=Active) ; BBh.1 + WLEX, 1, // Wireless LAN (0=Not Exist, 1=Exist) ; BBh.2 + BTEX, 1, // BlueTooth (0=Not Exist, 1=Exist) ; BBh.3 + KLSW, 1, // Kill Switch (0=Off, 1=On) ; BBh.4 + WLOK, 1, // Wireless LAN Initialize OK ; BBh.5 + AT3G, 1, // 3G (0=non-active, 1=active) ; BBh.6 + EX3G, 1, // 3G (0=Not Exist, 1=Exist) ; BBh.7 + PJID, 8, // Project ID ; BCh + CPUJ, 3, // CPU Type ; BDh.0-2 + // 00, Tj85, + // 01, Tj90, + // 02, Tj100, + // 03, Tj105, + // 04 - 07, Reserved + CPNM, 3, // CPU Core number ; BDh.3-5 + // 00, Single Core + // 01, Dual Core + // 02, Quad Core + // 03 - 07, Reserved + GATY, 2, // VGA Type ; BDh.6-7 + // 00, UMA + // 01. Discrete + // 02 - 03, Reserved + Offset(0xBE), + BOL0, 1, // Batt0 (0=OffLine, 1=OnLine) ; BEh.0 + BOL1, 1, // Batt1 (0=OffLine, 1=OnLine) ; BEh.1 + , 2, // Reserved ; BEh.2-3 + BCC0, 1, // Batt0 be charging (1=Charging) ; BEh.4 + BCC1, 1, // Batt1 be charging (1=Charging) ; BEh.5 + , 2, // Reserved ; BEh.6-7 + BPU0, 1, // Batt0 (1=PowerUp) ; BFh.0 + BPU1, 1, // Batt1 (1=PowerUp) ; BFh.1 + , 2, // Reserved ; BFh.2-3 + BOS0, 1, // Batt0 (1=OnSMBUS) ; BFh.4 + BOS1, 1, // Batt1 (1=OnSMBUS) ; BFh.5 + , 2, // Reserved ; BFh.6-7 + Offset(0xC0), + BTY0, 1, // Batt Type (0=NiMh, 1=LiIon) ; C0h.0 + BAM0, 1, // Battery mode (0=mA, 1=mW) ; C0h.1 + BAL0, 1, // Low Battery ; C0h.2 + , 1, // Reserved ; C0h.3 + BMF0, 3, // Battery Manufacturer ; C0h.4-6 + // 001 : Sanyo + // 010 : Sony + // 100 : Pansonic + // 101 : CPT + , 1, // Reserved ; C0h.7 + BST0, 8, // Battery Status ; C1h + // Bit0 : Discharging + // Bit1 : Charging + // Bit2 : Discharg and Critical Low + // Bit3-7 : Reserved + BRC0, 16, // Batt Remaining Capacity ; C2h, C3h + BSN0, 16, // Batt Serial Number ; C4h, C5h + BPV0, 16, // Batt Present Voltage ; C6h, C7h + BDV0, 16, // Batt Design Voltage ; C8h, C9h + BDC0, 16, // Batt Design Capacity ; CAh, CBh + BFC0, 16, // Batt Last Full Charge Capacity ; CCh, CDh + GAU0, 8, // Batt Gasgauge ; CEh + CYC0, 8, // Batt Cycle Counter ; CFh + BPC0, 16, // Batt Current ; D0h, D1h + BAC0, 16, // Batt Average Current ; D2h, D3h + BTW0, 8, // Batt Comsuption ; D4h + BVL0, 8, // Batt Battery Volt ; D5h + BTM0, 8, // Batt Battery Temp ; D6h + BAT0, 8, // Batt Average Temp (Degree C) ; D7h + BCG0, 16, // Batt charge current ; D8h, D9h + BCT0, 8, // Batt Current Temp Semple counter ; DAh + BCI0, 8, // BATT CMD Index for read BATT(SMB) ; DBh + BCM0, 8, // Count up to Communicate BATT ; DCh + BOT0, 8, // Count up if BATT over Temp ; DDh + BSSB, 16, // BATT Battery Status SMB ; DEh, DFh + BOV0, 8, // BATT Over Voltage Count ; E0h + BCF0, 8, // BATT Communication Fail Counter ; E1h + BAD0, 8, // Battery Voltage of ADC ; E2h + BCV1, 16, // Cell Voltage 1 (mV) ; E3h, E4h + BCV2, 16, // Cell Voltage 2 (mV) ; E5h, E6h + BCV3, 16, // Cell Voltage 3 (mV) ; E7h, E8h + BCV4, 16, // Cell Voltage 4 (mV) ; E9h, EAh + Offset(0xF4), + BMD0, 16, // Manufacture Date ; F4h, F5h + // Batt Day ; BIT[4:0] (Day) + // Batt Month ; BIT[9:5] (Month) + // Batt Year ; BIT[15:10] (Year) + BACV, 16, // Charging Voltage ; F6h, F7h + BDN0, 8, // Battery Cell Number ; F8h + , 8 // Last byte for Reserved. + } + + Method (_CRS, 0, NotSerialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + Return (ECMD) + } + + Method (_REG, 2, NotSerialized) + { + // Initialize AC power state + Store (ADPT, \PWRS) + + // Initialize LID switch state + Store (GP15, \LIDS) + + // Force a read of CPU temperature + Store (CTML, Local0) + } + + +/* + * EC Query Responses + * + * DTS temperature update 10h + * Decrease brightness event 11h + * Increase brightness event 12h + * Cover lid open 15h + * Cover lid close 16h + * External device plugged 17h + * External device removed 18h + * Bluetooth wake up event 19h + * Scr expand event 1Bh + * Display toggle 1Ch + * CPU fast/slow event 1Dh + * Battery in critical low 22h + * Battery in low state 23h + * Battery pack plug in 25h + * Docking in 2Ah + * Undock 2Bh + * Power button pressed 32h + * AC plug in 37h + * AC removed 38h + * Modem ring in 3Ah + * PME signal active 3Eh + * Hotkey make Function 45h + * Hotkey break Function 46h + */ + + // AC Power Connected + Method (_Q37, 0, NotSerialized) + { + Store (One, \PWRS) + Notify (AC, 0x80) + Notify (BATX, 0x80) + // TODO ADD CPU power profile + \PNOT () + } + + // AC Power Removed + Method (_Q38, 0, NotSerialized) + { + Store (Zero, \PWRS) + Notify (AC, 0x80) + Notify (BATX, 0x80) + // TODO ADD CPU power profile + \PNOT () + } + + // Battery at critical low state + Method (_Q22, 0, NotSerialized) + { + Notify (BATX, 0x80) + } + + // Battery insert + Method(_Q25, 0, NotSerialized) + { + Notify(BATX, 0x81) + Notify(BATX, 0x80) + } + + // Commuation Device Disable/Enable Event + Method(_Q60, 0, NotSerialized) + { + IF(WLEX) //if Wlan exist + { + //TODO Store(WLAT, LANE) + } + } + + #include "ac.asl" + #include "battery.asl" +} diff --git a/src/ec/compal/ene932/acpi/superio.asl b/src/ec/compal/ene932/acpi/superio.asl new file mode 100644 index 0000000..db4b412 --- /dev/null +++ b/src/ec/compal/ene932/acpi/superio.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is _SB.PCI0.LPCB + +Device (SIO) { + Name (_UID, 0) + Name (_ADR, 0) + + +#ifdef SIO_EC_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + } + EndDependentFn () + }) + } +#endif +} diff --git a/src/ec/compal/ene932/chip.h b/src/ec/compal/ene932/chip.h new file mode 100644 index 0000000..5d209ff --- /dev/null +++ b/src/ec/compal/ene932/chip.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _EC_COMPAL_ENE932_CHIP_H +#define _EC_COMPAL_ENE932_CHIP_H + +#include <device/device.h> +#include <pc80/keyboard.h> + +struct chip_operations; +extern struct chip_operations ec_compal_ene932_ops; + +struct ec_compal_ene932_config { + struct pc_keyboard keyboard; +}; + +#endif /* _EC_COMPAL_ENE932_CHIP_H */ diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c new file mode 100644 index 0000000..c3087e9 --- /dev/null +++ b/src/ec/compal/ene932/ec.c @@ -0,0 +1,180 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __PRE_RAM__ + +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include <stdlib.h> +#include <arch/io.h> +#include <delay.h> +#include "ec.h" +#include "chip.h" + +/* kbc helper functions from drivers/pc80/keyboard.c. TODO: share functions. */ +static int kbc_input_buffer_empty(void) +{ + u32 timeout; + for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) & KBD_IBF); + timeout--) { + mdelay(1); + } + + if (!timeout) { + printk(BIOS_WARNING, + "Unexpected Keyboard controller input buffer full\n"); + } + return !!timeout; +} + + +static int kbc_output_buffer_full(void) +{ + u32 timeout; + for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(KBD_STATUS) + & KBD_OBF) == 0); timeout--) { + mdelay(1); + } + + if (!timeout) { + printk(BIOS_INFO, "Keyboard controller output buffer result timeout\n"); + } + return !!timeout; +} + +int kbc_cleanup_buffers(void) +{ + u32 timeout; + for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) + & (KBD_OBF | KBD_IBF)); timeout--) { + mdelay(1); + inb(KBD_DATA); + } + + if (!timeout) { + printk(BIOS_ERR, "Couldn't cleanup the keyboard controller buffers\n"); + printk(BIOS_ERR, "Status (0x%x): 0x%x, Buffer (0x%x): 0x%x\n", + KBD_STATUS, inb(KBD_STATUS), KBD_DATA, inb(KBD_DATA)); + } + + return !!timeout; +} + + +/* The ENE 60/64 EC registers are the same comand/status IB/OB KBC pair. + * Check status from 64 port before each command. + * + * Ex. Get panel ID command C43/D77 + * Check IBF empty. Then Write 0x43(CMD) to 0x64 Port + * Check IBF empty. Then Write 0x77(DATA) to 0x60 Port + * Check OBF set. Then Get Data(0x03:panel ID) from 0x60 + * Different commands return may or maynot respond and may have multiple + * bytes. Keep it simple for nor + */ + +u8 ec_kbc_read_ob(void) +{ + if (!kbc_output_buffer_full()) return 0; + return inb(KBD_DATA); +} + +void ec_kbc_write_cmd(u8 cmd) +{ + if (!kbc_input_buffer_empty()) return; + outb(cmd, KBD_COMMAND); +} + +void ec_kbc_write_ib(u8 data) +{ + if (!kbc_input_buffer_empty()) return; + outb(data, KBD_DATA); +} + + +/* + * These functions are for accessing the ENE932 device space, but are not + * currently used. + */ +/* +static u8 ec_io_read(u16 addr) +{ + outb(addr >> 8, EC_IO_HIGH); + outb(addr & 0xff, EC_IO_LOW); + return inb(EC_IO_DATA); +} +*/ +/*static void ec_write(u16 addr, u8 data) +{ + outb(addr >> 8, EC_IO_HIGH); + outb(addr & 0xff, EC_IO_LOW; + outb(data, EC_IO_DATA); +} +*/ + +#ifndef __SMM__ +static void ene932_init(device_t dev) +{ + struct ec_compal_ene932_config *conf = dev->chip_info; + + + if (!dev->enabled) + return; + + printk(BIOS_DEBUG, "Compal ENE932: Initializing keyboard.\n"); + pc_keyboard_init(&conf->keyboard); + +} + + +static void ene932_read_resources(device_t dev) +{ + /* This function avoids an error on serial console. */ +} + + +static void ene932_enable_resources(device_t dev) +{ + /* This function avoids an error on serial console. */ +} + +static struct device_operations ops = { + .init = ene932_init, + .read_resources = ene932_read_resources, + .enable_resources = ene932_enable_resources +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, 0, 0, { 0, 0 }, } +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), + pnp_dev_info); +} + +struct chip_operations ec_compal_ene932_ops = { + CHIP_NAME("COMPAL ENE932 EC") + .enable_dev = enable_dev +}; +#endif /* ! __SMM__ */ +#endif /* ! __PRE_RAM__ */ diff --git a/src/ec/compal/ene932/ec.h b/src/ec/compal/ene932/ec.h new file mode 100644 index 0000000..879925f --- /dev/null +++ b/src/ec/compal/ene932/ec.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * EC communication interface for COMPAL ENE932 Embedded Controller. + */ + +#ifndef _EC_COMPAL_ENE932_EC_H +#define _EC_COMPAL_ENE932_EC_H + +#define EC_IO 0xfd60 /* Mainboard specific. Could be Kconfig option */ +#define EC_IO_HIGH EC_IO + 1 +#define EC_IO_LOW EC_IO + 2 +#define EC_IO_DATA EC_IO + 3 + +/* ENE EC internal address space */ +#define REG_SPI_DATA 0xfeab +#define REG_SPI_COMMAND 0xfeac +#define REG_SPI_CONFIG 0xfead +#define CFG_CSn_FORCE_LOW (1 << 4) +#define CFG_COMMAND_WRITE_ENABLE (1 << 3) +#define CFG_STATUS (1 << 1) + + +#define KBD_DATA 0x60 +#define KBD_COMMAND 0x64 +#define KBD_STATUS 0x64 +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) + + +/* Wait 400ms for keyboard controller answers */ +#define KBC_TIMEOUT_IN_MS 400 + +u8 ec_kbc_read_ob(void); +void ec_kbc_write_cmd(u8 cmd); +void ec_kbc_write_ib(u8 data); +int kbc_cleanup_buffers(void); + +#endif /* _EC_COMPAL_ENE932_EC_H */