On Thu, Apr 30, 2009 at 03:58:42PM +0200, svn@coreboot.org wrote:
Author: stepan Date: 2009-04-30 15:58:42 +0200 (Thu, 30 Apr 2009) New Revision: 4238
[...]
Modified: trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c
--- trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -163,6 +163,12 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +/* maximum size of high tables in KB */ +#define HIGH_TABLES_SIZE 64 +extern uint64_t high_tables_base, high_tables_size; +#endif
static void pci_domain_set_resources(device_t dev) { /* The order is important to find the correct RAM size. */ @@ -199,6 +205,13 @@ /* The PCI hole does does not overlap the memory. */ tolmk = tomk; }
+#if HAVE_HIGH_TABLES == 1
high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
high_tables_size = HIGH_TABLES_SIZE* 1024;
printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+#endif
The above is not correct. It places the high tables over the vga memory.
-Kevin