[coreboot] #203: [Coreboot] Misalignment with GCC 4.9.1

[coreboot]

#203: [Coreboot] Misalignment with GCC 4.9.1
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    Reporter:  Ryan Lin     |         Owner:  stepan@…
        Type:  enhancement  |        Status:  new
    Priority:  major        |     Milestone:
   Component:  coreboot     |      Keywords:
Dependencies:               |  Patch Status:  there is no patch
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 Hello Coreboot,

I compiled coreboot with GCC 4.9.1 for x86 system, and found a
 misalignment issue. :

Here is the abnormal segment of ramstage.map:

0001d1d0 T _bs_init_begin
 0001d1e0 t mrc_cache_update
 0001d200 t pch_log
 0001d220 t finalize
 0001d248 t spi_init_bscb
 0001d25c t cbmem_bscb
 0001d280 t disable_rom_cache_bscb
 0001d2a8 T _bs_init_end

Issue 1 : the address of "mrc_cache_update" should be 0001d1d0, but it is
 shifted to 0001d1e0.
 Issue 2 : the size of "mrc_cache_update" is 20 bytes, so the start adress
 of "pch_log" should be 0001d1f4, but it is shifted to 0001d200.

Does there any compiler options need to be added for GCC 4.9.1?

Thank you,
 Ryan