21 May
2007
21 May
'07
7:51 p.m.
The code was enabling interrupts for the serial port, possibly causing random hangs on boot. I have replaced the 8250 initialisation code with that in uart8250.c
Signed-off-by: Ben Hewson ben@hewson-venieri.com
----------------------------------------------------------------------------------------------------------------------
Doh !
This seems to work ok for me, but I can't say for sure if it has stopped the random boot hangs, as they were/are a bit random.
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Index: src/southbridge/via/vt8231/vt8231_early_serial.c
===================================================================
--- src/southbridge/via/vt8231/vt8231_early_serial.c (revision 2682)
+++ src/southbridge/via/vt8231/vt8231_early_serial.c (working copy)
@@ -54,22 +54,17 @@
vt8231_writesuper(0xf4, 0xfe);
// enable serial out
vt8231_writesuper(0xf2, 7);
- // That's it for the sio stuff.
- // movl $SUPERIOCONFIG, %eax
- // movb $9, %dl
- // PCI_WRITE_CONFIG_BYTE
- // set up reg to set baud rate.
- vt8231_writesiobyte(0x3fb, 0x80);
- // Set 115 kb
- vt8231_writesioword(0x3f8, 1);
- // Set 9.6 kb
- // WRITESIOWORD(0x3f8, 12)
- // now set no parity, one stop, 8 bits
- vt8231_writesiobyte(0x3fb, 3);
- // now turn on RTS, DRT
- vt8231_writesiobyte(0x3fc, 3);
- // Enable interrupts
- vt8231_writesiobyte(0x3f9, 0xf);
- // should be done. Dump a char for fun.
- vt8231_writesiobyte(0x3f8, 48);
+
+ /* disable interrupts */
+ outb(0x0, TTYS0_BASE + UART_IER);
+ /* enable fifo's */
+ outb(0x01, TTYS0_BASE + UART_FCR);
+ /* assert DTR and RTS so the other end is happy */
+ outb(0x03, TTYS0_BASE + UART_MCR);
+ /* Set Baud Rate Divisor to 1 ==> 115200 Baud */
+ outb(0x80 | TTYS0_LCS, TTYS0_BASE + UART_LCR);
+ outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
+ outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
+ outb(TTYS0_LCS, TTYS0_BASE + UART_LCR);
+
}