Peter Stuge wrote:
On Sun, Apr 29, 2007 at 11:39:01PM +0200, Quux wrote:
Those two pdf's just show photo's,
Oh. :(
I guess it is pretty much established, that it's all about two plcc in parallel with #CE activated individually. not that difficult after all.
Definately. This goes for any flash. I made http://stuge.se/ceswitch.png when discussing this with Anton Borisov.
(Note only one switch should be closed at a time. I had no better symbol at hand.)
using a flip over socket avoids cutting the #CE line on the mobo if there is no chipset output driving those 2 #CE signals.
True, but there usually is.. Right? This is especially true on buses where more than one device is attached. E.g. LPC, with both the flash and a superio.
The #CE signal on the flash device is active when the signal is LOW. That is what the # in front of the CE stands for. The #CE voltage is pulled high via a pull-up resistor to the VCC rail of the flash device. The driving signal from the chipset is an open drain on an output buffer FET. The FET actually just pulls down or sinks the current from the pull-up resistor to alow level when the #CE is active. The chipset doesn't supply a high or low level voltage tothe flash device #CE pin.
I'll post a pdf schematic shortly. I hope this ends all the confusion about this.
-Bari