Zheng Bao (zheng.bao@amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2304
-gerrit
commit bc3fd08824e572377f8093dc40db7980d64b6563 Author: Zheng Bao fishbaozi@gmail.com Date: Sun Feb 10 21:20:39 2013 +0800
AMD S3: Add missing erasing flash sector for saving MTRR register
It has worked up to now because the region is already erased the first time the board boots, and every additional boot the same data is being written over the old data.(by Dave Frodin)
Change-Id: Id334c60668e31d23c1d552d0ace8eb6ae5513e6b Signed-off-by: Zheng Bao zheng.bao@amd.com Signed-off-by: zbao fishbaozi@gmail.com --- src/cpu/amd/agesa/s3_resume.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 7069c77..5b4c2c3 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -168,6 +168,8 @@ void OemAgesaSaveMtrr(void) flash->spi->rw = SPI_WRITE_FLAG; spi_claim_bus(flash->spi);
+ flash->erase(flash, S3_DATA_MTRR_POS, S3_DATA_MTRR_SIZE); + /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;