I just realized a potential problem for you guys that are going to try LB on 440bx systems.
The Bitworks IMS board useses a 66Mhz front side bus but the chipset can do 100Mhz. I suspect that most of these commercial mainboards will be useing 100Mhz.
Pretty much all the memory settings in the northbridge are the default which I think are the 66Mhz settings. Only the stuff that is read out of the SPD is configured.
At 100Mhz the settings for the Memory strength buffers are much toucher. (According to an Intel rep) so if your board runs with a FSB of 100Mhz RAM may not be reliable for you or may not work at all. Be sure to give it a good test with memtest.
I don't know a lot about the memory strength settings but I'll try to help. I debugged the original memory setup by comparing config space dumps of a Comercial BIOS Northbridge settings vs what LB was doing.
Before you flash in LB get a lspci -xxx of the north bridge settings with 'lspci -s 0 -xxx' so you can compare.
Also the smbus controller is in the southbridge and thats what reads the SPD settings out of the RAM. So far all the lspci listings I have seen have the southbridge at Dev 07 which should work but if your southbridge shows up somewhere else then you will have to set the PIIX4_DEVFN option for memory SPD reading to work.
This also assumes your mainboard Mfg hasn't done something flaky with the SMbus.