Hello
I am new to coreboot. I tried to run coreboot on my Thinkpad W520 to replace my Sandy Bridge CPU by a Ivy Bridge CPU, since several people reported it worked very well.
Following their suggestions, I simply tried to flash a T520 image to save time. It didn't work at all. I was very angry I had wasted almost 2 days doing that. So I took the time to port coreboot to the Thinkpad W520 following the specs from http://kythuatphancung.vn/uploads/download/5165b_Wistron_Kendo-3_WS_-_10222-... and explore the issues I had (black screen, no boot)
First, please find the patch attached to add support to the Thinkpad W520 mainboard. This patch is based on the T520 mainboard as the W520 is very close. However, it needed romstage additions for ram init (cf p103 of the pdf)
I can now boot with various combinations of population of the Dimm slots, with the 4 slots all working, and the Dimm correctly identified by memtest
However, I can not use my normal 8Gb Dimm sticks. One of them work, but 2x8Gb does not work most of the time. I get errors in memtest when I am lucky to boot. The sticks are DDR3L 2133 (bus speed 1066 MHz) and they worked fine with the bios 1.36: I tested the sticks for over 24h with memtest86 7.1 just a week ago to check how hot my old CPU would get.
After further investigation, if I run memtest86 7.1 on the bios 1.36, it shows the correct information and timings: tCL-tRCD-tRP-tRAS are 11-11-11-29, and the RAM is running at 1066MHz.
If I run memtest86 on coreboot, it shows the RAM is running at 931MHz with timings 10-10-10-28. All this would be fine if it didn't cause errors on the memtest86! It looks like the SPD decoding is buggy, and instead of using the optimal configuration (11-11-11) coreboot picks the next one.
I would be happy to fix that but I don't know where to look. I correctly put max_mem_clock_mhz = 1066 in devicetree.cb so I don't understand. Can I hardcode timing settings? Is there any other place I should check for SPD issues?
There are some other W520 specific issues. I will try to prepare a wiki page to explain them. The big ones are: - the bottom plastic case is conductive: if you add a J100 header, you must trim the ends or you will have shorts and the computer will not boot - if you flash with a raspberry pi, you do not need external power. the 3V from pin 17 are enough. WP and HOLD can be left floating if you want. But you must insert all the pins at once, otherwise the W25Q64 may not respond (it is weird, I see no logical reason, but it works reliably) - native graphics initialization gave me video artifacts in seabios. Using the VGA bios fixed that
On https://www.coreboot.org/Board:lenovo/t520 I see issues: yellow USB port isn't powered in power-off state. DisplayPort only connected to Discrete GPU TPM. At the moment there is only basic support inside coreboot... Boot time issues ( keyboard rest timeout ) ultrabay hot plug (event missing?) some power management states missing
I am new to coreboot. I could try to add the missing power management states. But can I please ask for pointers and suggestions? What is missing? Is there any documentation?
Also, in romstage I am not sure of : /* Disable unused devices (board specific) */ RCBA32(FD) = 0x1ee51fe3;
The W520 is a bit different from a t420 and I think it may not be the same. How do I compute this number?
Also, can I please ask for some help on USBDEBUG? I have a FT232R cable and enabled CONFIG_USBDEBUG_DONGLE_FTDI_FT232H. But I receive nothing. Is it necessary to have a FT232H? I looked at the code and it does not seem very specific. Having debug information would be helpful to fix these ram issues.
Charlotte