Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454
-gerrit
commit 13ac7a9e4ed6cba54a049f584a87aabfa82756bc Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Wed Feb 1 15:33:39 2012 +0200
Add support for RAM-less multi-processor init
For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM.
The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB.
The symbol ap_sipi_vector is exported as CONFIG_AP_SIPI_VECTOR and will be used by a cache_as_ram.inc with hyper-threading support.
Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/arch/x86/Makefile.inc | 9 +++++++-- src/arch/x86/init/ldscript_failover.lb | 12 ++++++++---- 2 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cbe38dd..36f9d3a 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -338,6 +338,11 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl $(OBJCOPY) --strip-debug $@ $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@
+$(obj)/bootblock_map.h: $(obj)/bootblock.elf + printf '#define CONFIG_AP_SIPI_VECTOR 0x' > $@ + grep ap_sipi_vector $(obj)/bootblock.map | colrm 9 >> $@ + printf '\n' >> $@ + ####################################################################### # Build the romstage $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld @@ -370,9 +375,9 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDI @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $@)/crt0.disasm
-$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S $(obj)/config.h $(obj)/build.h +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S $(obj)/config.h $(obj)/build.h $(obj)/bootblock_map.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -include $(obj)/build.h -include $(obj)/bootblock_map.h -I. -I$(src) $< -o $@
seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..052e0c5 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,18 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); + . = ALIGN(4096); ROMLOC = .; } >rom = 0xff
/* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +52,10 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment");
/DISCARD/ : { *(.comment)