Author: rminnich Date: 2008-08-24 05:27:28 +0200 (Sun, 24 Aug 2008) New Revision: 809
Modified: coreboot-v3/device/hypertransport.c coreboot-v3/mainboard/amd/serengeti/mainboard.h coreboot-v3/northbridge/amd/k8/coherent_ht.c coreboot-v3/northbridge/amd/k8/domain.c coreboot-v3/northbridge/amd/k8/incoherent_ht.c coreboot-v3/northbridge/amd/k8/raminit.c coreboot-v3/southbridge/amd/amd8111/acpi.c coreboot-v3/southbridge/amd/amd8111/lpc.c Log: If you get a warning, it's because you SHOULD be getting a warning.
next step is to fix up this: LAR build/coreboot.rom Bootblock coreboot.bootblock does not appear to be a bootblock. Error adding the bootblock to the LAR. make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 1 make: exit 2
Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/device/hypertransport.c =================================================================== --- coreboot-v3/device/hypertransport.c 2008-08-24 02:59:05 UTC (rev 808) +++ coreboot-v3/device/hypertransport.c 2008-08-24 03:27:28 UTC (rev 809) @@ -117,18 +117,19 @@ static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned int pos) { - static const u8 link_width_to_pow2[] = { 3, 4, 0, 5, 1, 2, 0, 0 }; - static const u8 pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; struct ht_link cur[1]; + int reset_needed; + int linkb_to_host; +#if OPT_HT_LINK == 1 unsigned int present_width_cap, upstream_width_cap; unsigned int present_freq_cap, upstream_freq_cap; + static const u8 link_width_to_pow2[] = { 3, 4, 0, 5, 1, 2, 0, 0 }; + static const u8 pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; unsigned int ln_present_width_in, ln_upstream_width_in; unsigned int ln_present_width_out, ln_upstream_width_out; unsigned int freq, old_freq; unsigned int present_width, upstream_width, old_width; - int reset_needed; - int linkb_to_host; - +#endif /* Set the hypertransport link width and frequency. */ reset_needed = 0; /* See which side of the device our previous write to
Modified: coreboot-v3/mainboard/amd/serengeti/mainboard.h =================================================================== --- coreboot-v3/mainboard/amd/serengeti/mainboard.h 2008-08-24 02:59:05 UTC (rev 808) +++ coreboot-v3/mainboard/amd/serengeti/mainboard.h 2008-08-24 03:27:28 UTC (rev 809) @@ -24,3 +24,4 @@ #define CPU_SOCKET_TYPE SOCKET_AM2 #define MEM_TRAIN_SEQ 0 /* for now */ #define HW_MEM_HOLE_SIZE_AUTO_INC 0 +#define HW_MEM_HOLE_SIZEK 0x100000
Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-24 02:59:05 UTC (rev 808) +++ coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-24 03:27:28 UTC (rev 809) @@ -1644,13 +1644,12 @@ printk(BIOS_SPEW, "done\r\n"); }
-int apply_cpu_errata_fixes(unsigned nodes) +int apply_cpu_errata_fixes(unsigned int nodes) { unsigned node; int needs_reset = 0; for(node = 0; node < nodes; node++) { u32 dev; - u32 cmd; dev = NODE_MC(node); } return needs_reset;
Modified: coreboot-v3/northbridge/amd/k8/domain.c =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c 2008-08-24 02:59:05 UTC (rev 808) +++ coreboot-v3/northbridge/amd/k8/domain.c 2008-08-24 03:27:28 UTC (rev 809) @@ -126,7 +126,7 @@ } } } -#if CONFIG_PCI_64BIT_PREF_MEM == 0 +#ifdef CONFIG_PCI_64BIT_PREF_MEM /* Initialize the system wide io space constraints */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); resource->base = 0x400; @@ -171,7 +171,7 @@ void disable_hoist_memory(unsigned long hole_startk, int i); u32 hoist_memory(unsigned long hole_startk, int i); #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#ifdef CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; struct resource *resource, *last; #endif @@ -188,7 +188,7 @@ io = find_resource(dev, 0); io->base = DEVICE_IO_START; #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#ifdef CONFIG_PCI_64BIT_PREF_MEM /* Now reallocate the pci resources memory with the * highest addresses I can manage. */ @@ -330,7 +330,7 @@ }
- printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08lx, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
Modified: coreboot-v3/northbridge/amd/k8/incoherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/incoherent_ht.c 2008-08-24 02:59:05 UTC (rev 808) +++ coreboot-v3/northbridge/amd/k8/incoherent_ht.c 2008-08-24 03:27:28 UTC (rev 809) @@ -394,8 +394,6 @@ u8 next_unitid, last_unitid; unsigned uoffs;
- int reset_needed = 0; - #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 /* let's record the device of last ht device, * So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE @@ -519,7 +517,9 @@
} while (last_unitid != next_unitid );
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 out: +#endif end_of_chain: ; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 @@ -718,7 +718,6 @@ unsigned regpos; u32 dword; u8 busn; - unsigned bus; unsigned offset_unitid = 0; reg = pci_conf1_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4);
Modified: coreboot-v3/northbridge/amd/k8/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-24 02:59:05 UTC (rev 808) +++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-24 03:27:28 UTC (rev 809) @@ -2264,8 +2264,6 @@ { u32 dword; u32 dwordx; - unsigned SlowAccessMode = 0; - long dimm_mask = meminfo->dimm_mask & 0x0f;
#if DIMM_SUPPORT==0x0104 /* DDR2 and REG */ @@ -2293,7 +2291,8 @@ #endif
#if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ - /* for UNBUF DIMM */ + unsigned SlowAccessMode = 0; + /* for UNBUF DIMM */ dword = 0x00111222; dwordx = 0x002f2f00; switch (meminfo->memclk_set) { @@ -2531,7 +2530,7 @@ #endif meminfo = &sysinfo->meminfo[ctrl->node_id];
- printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :0x%x\n", paramx); + printk(BIOS_DEBUG, "FIXME sdram_set_spd_registers: paramx :%p\n", ¶mx); activate_spd_rom(ctrl); dimm_mask = spd_detect_dimms(ctrl); @@ -2749,7 +2748,6 @@ print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]); #endif - u32 dword;
/* Error if I don't have memory */ if (memory_end_k(ctrl, controllers) == 0) { @@ -2758,7 +2756,7 @@
/* Before enabling memory start the memory clocks */ for(i = 0; i < controllers; i++) { - u32 dtl, dch; + u32 dch; if (!sysinfo->ctrl_present[ i ]) continue; dch = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); @@ -2779,11 +2777,10 @@
/* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */ memreset(controllers, ctrl); -#if 0 +#if 1 printk(BIOS_DEBUG, "prepare to InitDram:"); for(i=0; i<10; i++) { - print_debug_hex32(i); - printk(BIOS_DEBUG, "\b\b\b\b\b\b\b\b"); + printk(BIOS_DEBUG, "%08x\b\b\b\b\b\b\b\b", i); } printk(BIOS_DEBUG, "\n"); #endif @@ -2839,7 +2836,7 @@ }
for(i = 0; i < controllers; i++) { - u32 dcl, dch, dcm; + u32 dcl, dcm; if (!sysinfo->ctrl_present[ i ]) continue; /* Skip everything if I don't have any memory on this controller */
Modified: coreboot-v3/southbridge/amd/amd8111/acpi.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-08-24 02:59:05 UTC (rev 808) +++ coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-08-24 03:27:28 UTC (rev 809) @@ -100,12 +100,12 @@ static void acpi_init(struct device *dev) { u8 byte; - u16 word; u16 pm10_bar; u32 dword; int on;
#if 0 + u16 word; printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. "); byte = pci_read_config8(dev, 0x49); pci_write_config8(dev, 0x49, byte | (1<<2));
Modified: coreboot-v3/southbridge/amd/amd8111/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-08-24 02:59:05 UTC (rev 808) +++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-08-24 03:27:28 UTC (rev 809) @@ -94,7 +94,7 @@ l = (unsigned long *) ioapic_base;
ioapicregvalues[0].value_high = bsp_apicid<<(56-32); - printk(BIOS_DEBUG, "amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "amd8111: ioapic bsp_apicid = %02lx\n", bsp_apicid); for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { @@ -119,7 +119,7 @@ pci_write_config32(dev,0xa0, 0xfed00001); hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe; - printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address); + printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); }