-jasonzhao
-----Original Message----- From: Rudolf Marek [mailto:r.marek@assembler.cz] Sent: Thursday, December 25, 2008 5:47 PM To: Jason Zhao Cc: Kevin O'Connor; Coreboot Subject: Re: [coreboot] [PATCH] SeaBIOS - vgahooks improvements
Hi Jason,
I'm reconnecting this to correct thread. Maybe you can set your settings for this conference to receive individual emails.
I had added some very similar code on my VX800 port, except the location of pci register that get speed of DDR2(mine is 0x90). I add those code in both vgahook.c of Seabios and vgabios.c of Coreboot
Do you have the 0x15 0x5f specification? I never succeeded to get it from Bruce.
Yes，I do, I have a spec named "Video BIOS External Interface Spec for UniChrome IGP". A 75 pages file. But it is confidential. (I can not understand why it is confidential). Maybe you can ask Bruce for getting this file from me(maybe he has no this file...).
Maybe 155f is VGABIOS dependent? Yesterday, I test two different VGABIOS on my VX800 board for my coreboot code. First one is extracted from legacy bios on board, which doesn't play with my 155fcallback(s3 resume fails). Second one (I don't know where it is from), however, seems work fine.
Yes seems so. Mine BIOS works also fine without any callback, but OpenChrome Drivers would not allow any other resolution than 640x480 complaining about low memory bandwidth.
return value of all int0x15(int21) AH AL Completion status ?? 5Fh Function call supported ?? !=5Fh Function not supported 00 5Fh Function call successful 01 5Fh Function call failed
Return value of 5f18. BL Bit[7:4] Memory Data Rate 0000: 66MHz 0001: 100MHz 0010: 133MHz 0011: 200MHz ( DDR200 ) 0100: 266MHz ( DDR266 ) 0101: 333MHz ( DDR333 ) 0110: 400MHz ( DDR400 ) 0111: 533MHz ( DDR I/II 533 1000: 667MHz ( DDR I/II 667) Bit[3:0] N: Frame Buffer Size 2^N MB
I studied both sides, VGA ROM BIOS and main BIOS Callbacks. It just writes the values of ebx from 0x5f18 to scratch registers.
Mine BIOS is: ruik@ruiktest:~/coreboot-merge-seabios-XP/coreboot-v2/zal$ strings 32301106.pci | head IBM COMPATIBLEBCPOST 03/01/07 PCIR VIA TRC63M *VT3336 Desktop NoTV Ver20
And finally I have one idea for the S3 resume. We do not need to call SeaBIOS again, we can jump to real mode, call the c000:0003 and then jump to waking vector directly. SeaBIOS will handle this directly for us without any S3 entrypoint ;)
Please see Kevin's newest reply for thread "[coreboot] 2 keypoints to use coreboot+seabios toachieveWINDOWS-XP's s3 sleep/resume". He said when S3 resume, coreboot can jump to f000:fff0 instead of jump into elf file. Although I didn’t test it yet.
Rudolf