Author: rminnich Date: 2008-10-09 17:11:52 +0200 (Thu, 09 Oct 2008) New Revision: 911
Removed: coreboot-v3/southbridge/amd/sb600/sb600.dts Modified: coreboot-v3/southbridge/amd/rs690/gfx.c coreboot-v3/southbridge/amd/rs690/ht.c coreboot-v3/southbridge/amd/rs690/pcie.c coreboot-v3/southbridge/amd/sb600/ac97.c coreboot-v3/southbridge/amd/sb600/hda.c coreboot-v3/southbridge/amd/sb600/ide.c coreboot-v3/southbridge/amd/sb600/lpc.c coreboot-v3/southbridge/amd/sb600/sata.c coreboot-v3/southbridge/amd/sb600/sb600.c coreboot-v3/southbridge/amd/sb600/sm.c coreboot-v3/southbridge/amd/sb600/usb.c Log: Fix the sb600 and rs690 code in the same way we just fixed the amd8111.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/southbridge/amd/rs690/gfx.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/rs690/gfx.c 2008-10-09 15:11:52 UTC (rev 911) @@ -571,6 +571,7 @@ .constructor = default_device_constructor, .phase2_setup_scan_bus = rs690_internal_gfx_enable, .phase3_scan = 0, + .phase4_enable_disable = rs690_enable, .phase4_read_resources = rs690_gfx_read_resources, .phase4_set_resources = rs690_gfx_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/rs690/ht.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/rs690/ht.c 2008-10-09 15:11:52 UTC (rev 911) @@ -87,6 +87,7 @@ .constructor = default_device_constructor, .phase2_setup_scan_bus = rs690_enable, .phase3_scan = 0, + .phase4_enable_disable = rs690_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/rs690/pcie.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-09 15:11:52 UTC (rev 911) @@ -399,6 +399,7 @@ .device = PCI_DEVICE_ID_ATI_RS690_PCIE}}}, .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, + .phase4_enable_disable = rs690_enable, .phase4_read_resources = pci_bus_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources,
Modified: coreboot-v3/southbridge/amd/sb600/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/ac97.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/ac97.c 2008-10-09 15:11:52 UTC (rev 911) @@ -38,6 +38,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_ACI}}}, .constructor = default_device_constructor, .phase3_scan = 0, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, @@ -51,6 +52,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_MCI}}}, .constructor = default_device_constructor, .phase3_scan = 0, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/sb600/hda.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/hda.c 2008-10-09 15:11:52 UTC (rev 911) @@ -279,6 +279,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_HDA}}}, .constructor = default_device_constructor, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/sb600/ide.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/ide.c 2008-10-09 15:11:52 UTC (rev 911) @@ -70,6 +70,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_IDE}}}, .constructor = default_device_constructor, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/sb600/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/lpc.c 2008-10-09 15:11:52 UTC (rev 911) @@ -213,6 +213,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = sb600_lpc_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = sb600_lpc_enable_resources,
Modified: coreboot-v3/southbridge/amd/sb600/sata.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/sata.c 2008-10-09 15:11:52 UTC (rev 911) @@ -193,6 +193,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB600_SATA}}}, .constructor = default_device_constructor, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/sb600/sb600.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sb600.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/sb600.c 2008-10-09 15:11:52 UTC (rev 911) @@ -201,16 +201,3 @@ deviceid); } } - -struct device_operations sb600 = { - .id = {.type = DEVICE_ID_PCI, - {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB600_LPC}}}, - .constructor = default_device_constructor, - .phase3_scan = 0, - .phase4_enable_disable = sb600_enable, - .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, - .phase6_init = NULL, - .ops_pci = &pci_dev_ops_pci, -};
Deleted: coreboot-v3/southbridge/amd/sb600/sb600.dts =================================================================== --- coreboot-v3/southbridge/amd/sb600/sb600.dts 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/sb600.dts 2008-10-09 15:11:52 UTC (rev 911) @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Ronald G. Minnich rminnich@gmail.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -{ - device_operations = "sb600"; -};
Modified: coreboot-v3/southbridge/amd/sb600/sm.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/sm.c 2008-10-09 15:11:52 UTC (rev 911) @@ -395,6 +395,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_SM}}}, .constructor = default_device_constructor, .phase3_scan = 0, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = sb600_sm_read_resources, .phase4_set_resources = sb600_sm_set_resources, .phase5_enable_resources = pci_dev_enable_resources,
Modified: coreboot-v3/southbridge/amd/sb600/usb.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-09 14:54:29 UTC (rev 910) +++ coreboot-v3/southbridge/amd/sb600/usb.c 2008-10-09 15:11:52 UTC (rev 911) @@ -205,6 +205,7 @@ .device = PCI_DEVICE_ID_ATI_SB600_USB2}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, + .phase4_enable_disable = sb600_enable, .phase4_read_resources = pci_dev_read_resources, .phase4_set_resources = usb_set_resources, .phase5_enable_resources = pci_dev_enable_resources,