Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1328
-gerrit
commit d07e775d85806855ce6acf5dda67682325e2952f Author: Duncan Laurie dlaurie@chromium.org Date: Fri Jun 29 15:38:02 2012 -0700
ELOG: Fix boot count increment for non-wake case
The count was only incrementing for a wake from S5 and it was not incrementing in the normal reboot case.
Change-Id: I73bc6db6bd02e6c4677f7e44a5c098c6dcb51747 Signed-off-by: Duncan Laurie dlaurie@google.com --- src/northbridge/intel/sandybridge/early_init.c | 11 ++++++----- 1 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 6bd774b..2954bf1 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -64,14 +64,15 @@ static void sandybridge_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
+ printk(BIOS_DEBUG, " done.\n"); + #if CONFIG_ELOG_BOOT_COUNT - /* Increment Boot Counter for non-S3 resume */ + /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); + ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) + return; + boot_count_increment(); #endif - - printk(BIOS_DEBUG, " done.\n"); }
static void sandybridge_setup_graphics(void)