Author: zbao Date: Fri Oct 8 07:08:47 2010 New Revision: 5923 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5923
Log: Trivial. Spell checking.
Signed-off-by: Zheng Bao zheng.bao@amd.com Acked-by: Zheng Bao zheng.bao@amd.com
Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.c Fri Oct 8 05:35:12 2010 (r5922) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c Fri Oct 8 07:08:47 2010 (r5923) @@ -30,7 +30,7 @@ * ordinarily in 64-bit mode. * * Trc precision does not use extra Jedec defined fractional component. - * InsteadTrc (course) is rounded up to nearest 1 ns. + * Instead Trc (course) is rounded up to nearest 1 ns. * * Mini and Micro DIMM not supported. Only RDIMM, UDIMM, SO-DIMM defined types * supported. @@ -183,7 +183,7 @@ * on setup options). It is the responsibility of PCI subsystem to * create an uncacheable IO region below 4GB and to adjust TOP_MEM * downward prior to any IO mapping or accesses. It is the same - * responsibility of the CPU sub-system prior toaccessing LAPIC. + * responsibility of the CPU sub-system prior to accessing LAPIC. * * Slot Number is an external convention, and is determined by OEM with * accompanying silk screening. OEM may choose to use Slot number @@ -655,7 +655,7 @@ {
/* Initiates a memory clear operation for all node. The mem clr - * is done in paralel. After the memclr is complete, all processors + * is done in parallel. After the memclr is complete, all processors * status are checked to ensure that memclr has completed. */ u8 Node; @@ -856,7 +856,7 @@ * HW memory clear process that the chip is capable of. The sooner * that dram init is set for all nodes, the faster the memory system * initialization can complete. Thus, the init loop is unrolled into - * two loops so as to start the processeses for non BSP nodes sooner. + * two loops so as to start the processes for non BSP nodes sooner. * This procedure will not wait for the process to finish. * Synchronization is handled elsewhere. */ @@ -878,7 +878,7 @@ reg = 0x78 + reg_off; val = Get_NB32(dev, reg); /* Setting this bit forces a 1T window with hard left - * pass/fail edge and a probabalistic right pass/fail + * pass/fail edge and a probabilistic right pass/fail * edge. LEFT edge is referenced for final * receiver enable position.*/ val |= 1 << DqsRcvEnTrain; @@ -1038,7 +1038,7 @@ } else { byte = mctRead_SPD(smbaddr, SPD_TRCRFC); if (byte & 0xF0) { - val++; /* round up in case fractional extention is non-zero.*/ + val++; /* round up in case fractional extension is non-zero.*/ } } if (Trc < val) @@ -1496,7 +1496,7 @@ DramConfigMisc = 0; DramConfigMisc2 = 0;
- /* set bank addessing and Masks, plus CS pops */ + /* set bank addressing and Masks, plus CS pops */ SPDSetBanks_D(pMCTstat, pDCTstat, dct); if (pDCTstat->ErrCode == SC_StopError) goto AutoConfig_exit; @@ -1582,7 +1582,7 @@ }
if (!(Status & (1 << SB_Registered))) - DramConfigLo |= 1 << UnBuffDimm; /* Unbufferd DIMMs */ + DramConfigLo |= 1 << UnBuffDimm; /* Unbuffered DIMMs */
if (mctGet_NVbits(NV_ECC_CAP)) if (Status & (1 << SB_ECCDIMMs)) @@ -3405,7 +3405,7 @@ if (pDCTstat->CSPresent & (1 << cs)) { odt &= ~(1 << (cs / 2));
- /* if quad-rank capable platform clear adtitional pins */ + /* if quad-rank capable platform clear additional pins */ if (max_dimms != MAX_CS_SUPPORTED) { if (pDCTstat->CSPresent & (1 << (cs + 1))) odt &= ~(4 << (cs / 2)); @@ -3768,7 +3768,7 @@ * Silicon Status: Fixed In Rev B0 * * Bug#15880: Determine validity of reset settings for DDR PHY timing. - * Solutiuon: At least, set WrDqs fine delay to be 0 for DDR2 training. + * Solution: At least, set WrDqs fine delay to be 0 for DDR2 training. */
for (Node = 0; Node < 8; Node++) {
Modified: trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Fri Oct 8 05:35:12 2010 (r5922) +++ trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Fri Oct 8 07:08:47 2010 (r5923) @@ -479,7 +479,7 @@ continue; }
- BanksPresent = 1; /* flag for atleast one bank is present */ + BanksPresent = 1; /* flag for at least one bank is present */ TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid); if (!valid) { print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4);
Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Fri Oct 8 05:35:12 2010 (r5922) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Fri Oct 8 07:08:47 2010 (r5923) @@ -656,7 +656,7 @@ {
/* Initiates a memory clear operation for all node. The mem clr - * is done in paralel. After the memclr is complete, all processors + * is done in parallel. After the memclr is complete, all processors * status are checked to ensure that memclr has completed. */ u8 Node; @@ -868,7 +868,7 @@ * HW memory clear process that the chip is capable of. The sooner * that dram init is set for all nodes, the faster the memory system * initialization can complete. Thus, the init loop is unrolled into - * two loops so as to start the processeses for non BSP nodes sooner. + * two loops so as to start the processes for non BSP nodes sooner. * This procedure will not wait for the process to finish. * Synchronization is handled elsewhere. */ @@ -1520,7 +1520,7 @@ DramConfigMisc = 0; DramConfigMisc2 = 0;
- /* set bank addessing and Masks, plus CS pops */ + /* set bank addressing and Masks, plus CS pops */ SPDSetBanks_D(pMCTstat, pDCTstat, dct); if (pDCTstat->ErrCode == SC_StopError) goto AutoConfig_exit; @@ -1547,7 +1547,7 @@ else val = 6; DramControl &= ~0xFF; - DramControl |= val; /* RdPrtInit = 6 for Cx CPU */ + DramControl |= val; /* RdPtrInit = 6 for Cx CPU */
if (mctGet_NVbits(NV_CLKHZAltVidC3)) DramControl |= 1<<16; /* check */ @@ -1570,7 +1570,7 @@ }
if (!(Status & (1 << SB_Registered))) - DramConfigLo |= 1 << UnBuffDimm; /* Unbufferd DIMMs */ + DramConfigLo |= 1 << UnBuffDimm; /* Unbuffered DIMMs */
if (mctGet_NVbits(NV_ECC_CAP)) if (Status & (1 << SB_ECCDIMMs)) @@ -3511,7 +3511,7 @@ * Silicon Status: Fixed In Rev B0 * * Bug#15880: Determine validity of reset settings for DDR PHY timing. - * Solutiuon: At least, set WrDqs fine delay to be 0 for DDR3 training. + * Solution: At least, set WrDqs fine delay to be 0 for DDR3 training. */ for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node;
Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c Fri Oct 8 05:35:12 2010 (r5922) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c Fri Oct 8 07:08:47 2010 (r5923) @@ -481,7 +481,7 @@ continue; }
- BanksPresent = 1; /* flag for atleast one bank is present */ + BanksPresent = 1; /* flag for at least one bank is present */ TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid); if (!valid) { print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4);