Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1324
-gerrit
commit b9eea92bd0015ce9d3fc461ec89cbcd2c4467912 Author: Stefan Reinauer reinauer@chromium.org Date: Thu Jun 28 12:22:28 2012 -0700
bd82x6x: Use CMOS variable if available for power-on on power failure
We used a hard coded value for some reason. Don't do that, but use CMOS instead.
Modelled after http://review.coreboot.org/#/c/443 to get bd82x6x in sync.
Change-Id: I36d715310157b9f9074f2a1c80710f85833020b4 Signed-off-by: Stefan Reinauer reinauer@google.com --- src/southbridge/intel/bd82x6x/smihandler.c | 14 ++++++++++---- 1 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 29f1a1e..da5b52b 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> +#include <pc80/mc146818rtc.h> #include "pch.h"
#include "nvs.h" @@ -324,11 +325,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat u8 reg8; u32 reg32; u8 slp_typ; - /* FIXME: the power state on boot should be read from - * CMOS or even better from GNVS. Right now it's hard - * coded at compile time. - */ u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + + // save and recover RTC port values + u8 tmp70, tmp72; + tmp70 = inb(0x70); + tmp72 = inb(0x72); + get_option(&s5pwr, "power_on_after_fail"); + outb(tmp70, 0x70); + outb(tmp72, 0x72); + void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep;
/* First, disable further SMIs */