Hi Nitin,
On 11.06.20 18:44, nitin.ramesh.singh@gmail.com wrote:
Flash start -> 0xFC000000 (with-in 4GB space @4227858432)
this is misleading. Setting it in the FMAP makes sense to make the calculations work, but the flash is not mapped there.
Because of other fixed resources below 0xff000000, the architectural limit of memory-mapped flash space is 16MiB. Some chipsets even limit the mapping to 8MiB. Without making changes to coreboot code (e.g. switch from memory mapped flash access to using the SPI controller), all coreboot regions have to fall into the memory mapped space.
Can any one please let me know what are the other changes required to incorporate the Coreboot image as per the given layout?
Generally, such a big CBFS seems odd. I think changes are better made outside of coreboot, e.g. the payload. What is your exact use case?
Nico