Hi, adding this section: register "lpc_ioe" = "LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_4E_4F" to devicetree.cb solved problem. Thanks!
пт, 9 сент. 2022 г. в 20:17, Nico Huber nico.h@gmx.de:
Hello Roman,
On 09.09.22 17:48, roman perepelitsin wrote:
I use coreboot for ApolloLake CPU (Atom). We have SuperIO WB83627-DHG
chip
on carrier board. LPC enabled, POST codes work normal. But I can't get access to SIO under Linux (via port 0x2e). Superiotool can't find chip. Also, I have CPLD on LPCB - I use it to view LPC transactions - so, then
I
try to out byte to 0x2e - transaction on LPC is none. But, I enable UART0 on SIO (via devicetree.cb) - and it works fine. Whats wrong?
the W83627DHG has the UART enabled by default, so it's still possible that coreboot can't access 0x2e either. Do you have a setting for `lpc_ioe` in your devicetree?
It's easier to help if you'd show your complete mainboard port.
Nico