On 17.03.2009 23:35, Myles Watson wrote:
2009/3/17 Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net:
The Pistachio and DBM690T ACPI code uses MMCONFIG to access southbridge PCI config registers. This fails because we explicitly disable MMCONFIG accesses with disable_pcie_bar3(). The comments in the code state that coreboot is expected to reenable MMCONFIG, but that never happens.
I think either of these options would be less ugly:
- Don't disable MMCONFIG.
The code comments around disable_pcie_bar3() indicate that the MMCONFIG address range may be relocated by the resource allocator (it is represented by a BAR) and relocating an active range is bad.
- Enable it in dev.init for the southbridge. (the equivalent of Phase 6 in v3.)
The RS690 BIOS developer's guide suggests that MMCONFIG should be used as early as possible and for all accesses involving the southbridge. I see two ways to achieve this: 1. Somehow tell the resource allocator that the MMCONFIG area is fixed and should not be relocated nor deactivated. Done. 2. If the MMCONFIG area should be relocatable (possible on RS690), make sure it gets special handling (disable directly before relocation, reenable directly after relocation).
Index: LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c
--- LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c (Revision 4010) +++ LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c (Arbeitskopie) @@ -36,7 +36,9 @@ #include <part/hard_reset.h> #include <part/init_timer.h> #include <boot/elf.h> +#include "../southbridge/amd/rs690/rs690.h"
/**
- @brief Main function of the DRAM part of coreboot.
@@ -49,6 +51,7 @@ void hardwaremain(int boot_complete) { struct lb_memory *lb_mem;
device_t nb_dev;why call it nb_dev when it's a southbridge?
Cut-n-paste code. A RS690 variant can be northbridge if it is attached to an Intel processor. That's unsupported by our code, though.
Regards, Carl-Daniel