On 27.03.2008 04:19, Jake Peavy wrote:
I'd be interested in trying to help with this effort. It would be certainly be a learning experience for me.
If Coreboot has been ported to PPC it might be very similar. Both PPC and MIPS architectures are RISC based, but maybe that's where the similarities end.
Well, only v2 has been ported to PPC and the structure of v3 is radically different. However, the v3 structure allows much easier porting, so I think v3 would be your preferred target.
Based on http://www.mips.com/media/files/MD00103-2B-4KE-SUM-02.04.pdfsection 6.1.5, MIPS execution begins at 0x1FC00000. At least on the MIPS32 core I have ;-)
I assume MIPS boards have some sort of ROM. How is that ROM mapped into the address space? Does execution begin at top of ROM, bottom of ROM or somewhere in between? That info is needed to check if our current ROM format (LAR) can handle MIPS or if we need to apply one of my patches.
You mentioned payload, is this typically the S1 (MBR) code in x86 arch?
It's a bit more complicated like that. A payload can either be a boot loader (like GRUB2/FILO) or an operating system (like Plan 9/Linux). It can also be some sort of bootloader-with-shell environment (like EFI/OpenFirmware) or something with a completely different scope (like Memtest).
Regards, Carl-Daniel