Author: stepan Date: 2007-05-11 01:50:27 +0200 (Fri, 11 May 2007) New Revision: 2659
Removed: trunk/LinuxBIOSv2/src/mainboard/via/epia-m/reset.c trunk/LinuxBIOSv2/src/mainboard/via/epia/reset.c Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Options.lb trunk/LinuxBIOSv2/src/mainboard/via/epia/Options.lb trunk/LinuxBIOSv2/targets/via/epia/Config.lb Log: Changes by Richard Smith and Peter Stuge from the LinuxBIOS symposium 2006.
With CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0, 1 million outb():s are used for timer calibration, which takes about one second.
All EPIA-M boards have timer2 so we use it to boot faster.
Only some EPIA boards have the Nehemiah CPU with timer2 so we default to IO calibration but add the TSC options so that they can be set in Config.lb.
src/mainboard/via/epia*/reset.c is dead code (entire file within #if 0) so we set HAVE_HARD_RESET=0 for both boards.
Signed-off-by: Peter Stuge peter@stuge.se Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/via/epia/Options.lb 2007-05-10 23:22:27 UTC (rev 2658) +++ trunk/LinuxBIOSv2/src/mainboard/via/epia/Options.lb 2007-05-10 23:50:27 UTC (rev 2659) @@ -11,6 +11,8 @@ uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET uses CONFIG_UDELAY_IO +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses HAVE_OPTION_TABLE uses USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD @@ -81,12 +83,15 @@ ## ## Build code to reset the motherboard from linuxBIOS ## -default HAVE_HARD_RESET=1 +default HAVE_HARD_RESET=0
## ## use io based udelay function +## disable IO and enable TSC on Nehemiah boards ## default CONFIG_UDELAY_IO=1 +default CONFIG_UDELAY_TSC=0 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
## ## Build code to export a programmable irq routing table
Deleted: trunk/LinuxBIOSv2/src/mainboard/via/epia/reset.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/via/epia/reset.c 2007-05-10 23:22:27 UTC (rev 2658) +++ trunk/LinuxBIOSv2/src/mainboard/via/epia/reset.c 2007-05-10 23:50:27 UTC (rev 2659) @@ -1,43 +0,0 @@ -#if 0 -//#include "arch/romcc_io.h" -#include <arch/io.h> - -typedef unsigned device_t; - -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x7) << 8)) - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void hard_reset(void) -{ - set_bios_reset(); - pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); -} -#endif
Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Options.lb 2007-05-10 23:22:27 UTC (rev 2658) +++ trunk/LinuxBIOSv2/src/mainboard/via/epia-m/Options.lb 2007-05-10 23:50:27 UTC (rev 2659) @@ -38,6 +38,7 @@ uses MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES @@ -66,11 +67,12 @@ ## Use TSC for udelay. ## default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## ## Build code to reset the motherboard from linuxBIOS ## -default HAVE_HARD_RESET=1 +default HAVE_HARD_RESET=0
## ## Build code to export a programmable irq routing table
Deleted: trunk/LinuxBIOSv2/src/mainboard/via/epia-m/reset.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/via/epia-m/reset.c 2007-05-10 23:22:27 UTC (rev 2658) +++ trunk/LinuxBIOSv2/src/mainboard/via/epia-m/reset.c 2007-05-10 23:50:27 UTC (rev 2659) @@ -1,43 +0,0 @@ -#if 0 -//#include "arch/romcc_io.h" -#include <arch/io.h> - -typedef unsigned device_t; - -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x7) << 8)) - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void hard_reset(void) -{ - set_bios_reset(); - pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); -} -#endif
Modified: trunk/LinuxBIOSv2/targets/via/epia/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/via/epia/Config.lb 2007-05-10 23:22:27 UTC (rev 2658) +++ trunk/LinuxBIOSv2/targets/via/epia/Config.lb 2007-05-10 23:50:27 UTC (rev 2659) @@ -1,6 +1,11 @@ # Sample config file for EPIA # This will make a target directory of ./epia
+## uncomment these three lines if you have a Nehemiah CPU to boot 1s faster +#option CONFIG_UDELAY_IO=0 +#option CONFIG_UDELAY_TSC=1 +#option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + target epia mainboard via/epia option MAXIMUM_CONSOLE_LOGLEVEL=9