Hi Nico,
On Sun, Jan 14, 2018 at 11:49 AM, Nico Huber nico.h@gmx.de wrote:
Hi,
On 14.01.2018 11:05, Kyösti Mälkki wrote:
On Sun, Jan 14, 2018 at 11:27 AM, Hal Martin hal.martin@gmail.com
wrote:
Just to verify again, I enabled all the PCI Express devices in the devicetree.cb to see if the missing devices would appear. Unfortunately
they
didn't.
The log says some of those PCIe root ports are hidden/disabled: PCI: Static device PCI: 00:1c.3 not found, disabling it.
You will want to look at your board's rcba_config() implementation for the enablement, it essentially takes precedence over anything you have in devicetree.cb. FD register 0x3418 should be of most interest to you, and there is also RPFN 0x0404 that affects the enumeration of 0:1c.0 PCIe root ports. Datasheet should be public.
Yep, they are disabled in `romstage.c`. I've commented on the commit that added the culprit.
Thank you for finding this! I pulled your changes in 23255 and now the PCIe devices are detected in coreboot: -[0000:00]-+-00.0 8086:0154 +-01.0-[01]----00.0 8086:10d3 +-01.1-[02]-- +-02.0 8086:0166 +-04.0 8086:0153 +-14.0 8086:1e31 +-19.0 8086:1502 +-1a.0 8086:1e2d +-1b.0 8086:1e20 +-1c.0-[03]----00.0 8086:10d3 +-1c.1-[04]----00.0 8086:0082 +-1c.2-[05]-- +-1c.3-[06]-- +-1c.4-[07]----00.0 10ec:8168 +-1c.5-[08]-- +-1c.6-[09]----00.0 8086:10d3 +-1c.7-[0a]----00.0 8086:10d3 +-1d.0 8086:1e26 +-1e.0-[0b]-- +-1f.0 8086:1e59 +-1f.2 8086:1e03 +-1f.3 8086:1e22 +-1f.5 8086:1e09 -1f.6 8086:1e24
Hal, generally you shouldn't set any register in your mainboard code that is already handled by the code for the respective chip (in this case sb/intel/bd82x6x/) unless you know what you are doing.
I definitely do not know what I'm doing in this case. This code in romstage.c came from autoport.
Given your changes to the PCH code in 23255, is it really helpful to have autoport setting this? Should autoport be setting PCIe device configuration in romstage.c at all? Or do we leave this to devicetree.cb and the PCH code?
-Hal
Nico