[coreboot] Patch set updated for coreboot: eb0e452 sb800: sata combine mode configure fix

[Kerry Sheh]

Kerry Sheh ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/229

-gerrit

commit eb0e4526ffeb1330d9c2b9f2c69cac6a4f3a41ec
Author: Kerry Sheh 
Date:   Mon Oct 10 18:23:49 2011 +0800

sb800: sata combine mode configure fix

Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to
    configure SataIdeCombinedMode is wrong.

sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller
      0: IDE controller is exposed and Combined Mode is enabled.
         SATA controller has control over Port0 through Port3,
         IDE controller has control over Port4 and Port5
      1: IDE controller is hidden and Combined Mode is disabled,
         SATA controller has full control of all 6 Ports when operating in non-IDE mode

Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250
    Signed-off-by: Kerry Sheh 
    Signed-off-by: Kerry Sheh 
---
 src/vendorcode/amd/cimx/sb800/SATA.c   |    4 ++--
 src/vendorcode/amd/cimx/sb800/SBTYPE.h |   10 ++++++++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
index 1c0e7e6..b7bbacd 100644
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ b/src/vendorcode/amd/cimx/sb800/SATA.c
@@ -470,7 +470,7 @@ sataInitAfterPciEnum (

if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
     // RIAD or AHCI
-    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
+    if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
       RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
       RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
       // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
@@ -631,7 +631,7 @@ sataInitLatePost (
   //Enable write access to pci header, pm capabilities
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);

-//  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
+//  if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);
 //  }
   sataBar5setting (pConfig, &ddBar5);
diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
index b8278cf..f8e825e 100644
--- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h
+++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
@@ -1106,6 +1106,16 @@ typedef unsigned int    CIM_STATUS;
  */
 #define CIMX_OPTION_ENABLED    1

+/**
+ * SATA_IDE_COMBINE_ENABLE  -Define  Enable Combined Mode
+ */
+#define SATA_IDE_COMBINE_ENABLE   0
+
+/**
+ * SATA_IDE_COMBINE_DISABLE  -Define  Disable Combined Mode
+ */
+#define SATA_IDE_COMBINE_DISABLE  1
+
 // mov al, code
 // out 80h, al
 // jmp $