On Tuesday 06 November 2007 00:51, Carl-Daniel Hailfinger wrote:
On 06.11.2007 00:40, Torsten Duwe wrote:
On Monday 05 November 2007, Carl-Daniel Hailfinger wrote:
What issues remain for the board now that this has been checked in?
[...]
- assumed write protect lines to the flash chips
IIRC we can flash PLCC boards under LB just fine, the SPI variants need to set one bit and allocate a port range in the SuperIO. Once I know how to tell board types apart, I can post a patch to fix that issue automatically.
Nope, flash erase fails reliably for me. I suggest we call it SPI flashing vs. LPC flashing for consistency's sake; there might be SPI chips in a PLCC housing out there?
My original idea was to say that gigabyte has one flash image for all board revisions, but SPI flashing alone will make them different, bit-wise.
- more possible issues due to GPIO and INT route programming...
This would be a lot easier with proper documentation.
Amen, brother!
'night Torsten