Issue #583 has been updated by Bill XIE.
File p8z77v-ifdprog-rdev.log added
Bill XIE wrote in #note-8:
Keith Hui wrote in #note-7:
IFD reflash process has been determined and implemented. Test underway. A mode where PCIEX16_3 operates in x2, not available with vendor BIOS, is added. Hardware has been tested to be capable of this mode, but PCIEX1_1 will be disabled.
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2070
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Affected versions: main * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB) p8z77v-ifd.bin (4 KB) p8z77v-ifdprog.log (103 KB) p8z77v-ifdprog-rdev.log (446 KB)