Re: [coreboot] Build Error since r4278

[Joseph Smith]

On Fri, 15 May 2009 14:25:54 -0700, ron minnich  wrote:
> another option (not at all tested, mind you; probably not quite right).
> Index: src/southbridge/intel/i82801xx/chip.h
>
> --- src/southbridge/intel/i82801xx/chip.h       (revision 4289)
> +++ src/southbridge/intel/i82801xx/chip.h       (working copy)
> @@ -43,7 +43,9 @@
>         uint8_t pirqf_routing;
>         uint8_t pirqg_routing;
>         uint8_t pirqh_routing;
> -};
>   uint8_t ide0_enable;
>   uint8_t ide1_enable;
>
> +}
>
> extern struct chip_operations southbridge_intel_i82801xx_ops;
> Index: src/southbridge/intel/i82801xx/i82801xx_ide.c
>
> --- src/southbridge/intel/i82801xx/i82801xx_ide.c       (revision 4289)
> +++ src/southbridge/intel/i82801xx/i82801xx_ide.c       (working copy)
> @@ -29,11 +29,12 @@
>
> static void ide_init(struct device *dev)
>  {
>   struct southbridge_intel_i82801xx_config *config =

dev->chip_info;
>     /* TODO: Needs to be tested for compatibility with ICH5(R). */
>     /* Enable IDE devices so the Linux IDE driver will work. */
>     uint16_t ideTimingConfig;
>   int enable_primary = 1;
>   int enable_secondary = 1;
>   int enable_primary = config->ide0_enable;
>   int enable_secondary = config->ide1_enable;
>
>   ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
>   ideTimingConfig &= ~IDE_DECODE_ENABLE;

yup something like that. But enable_primary and enable_secondary are
misleading and we would like to completely change them. Also we would want
the defaults to be "1" for those boards where ide0_enable and ide1_enable
is not specified.