Hello folks,
I have two questions for the code base in coreboot-v2.
1) In an effort to understand how the L2 cache in a PII processor can be activated, I wished to use the machine instruction 'invd'. It is implemented in src/include/cpu/x86/cache.h, but does not even compile as it stands. I had to remove that inexplicable addition '::: "memory"' in order to compile a rom image:
static inline void invd(void) { /* asm volatile("invd" ::: "memory"); */ asm volatile("invd"); }
I have never seen the attribute before, so I wonder if it is some kind of safe guard. Anyway, my idea was to use
static inline void enable_cache(void) { unsigned long cr0; cr0 = read_cr0(); cr0 &= 0x9fffffff; invd(); /* NEW */ write_cr0(cr0); wbinvd(); /* NEW */ }
since 'the Programmer's Guide vol. 3A/3B' gives no clues on methods for activating the L2 cache. However, nothing improved.
2) Has it been judged superfluous to support configuration entries such as
device pci 7.2 on # USB io 0x20 = 0x0000e001ul irq 0x3c = 0x0a end
on grounds that pci-devices _can_ do auto detection? I inserted two instances of 'print_debug' to make sure that pci_set_resources() is executed for the USB Host Controler, but the above specification never came into action. Were they even parsed?
Kind regards
Mats Erik Andersson