[coreboot] r867 - in coreboot-v3: mainboard/amd/serengeti northbridge/amd/k8

Author: rminnich
Date: 2008-09-18 18:45:46 +0200 (Thu, 18 Sep 2008)
New Revision: 867

Modified:
   coreboot-v3/mainboard/amd/serengeti/dts
   coreboot-v3/northbridge/amd/k8/domain.c
   coreboot-v3/northbridge/amd/k8/pci.c
Log:
This set of changes adds new nodes to dts that are required, adds
some prints, and fixes a null pointer deref bug that has been in the 
k8 code since the dawn of time.

We get here:

CPU 804 Mhz
Etherboot 5.4.3 (GPL) http://etherboot.org
Drivers: VIA-VELOCITY/PCI   Images: ELF   
Protocols: DHCP TFTP 
Relocating _text from: [000100e0,000349c0) to [0007b720,000a0000)
Boot from (N)etwork or (Q)uit?

Probing pci nic...
Probing isa nic...
<sleep>

Signed-off-by: Ronald G. Minnich 
Acked-by: Ronald G. Minnich

Modified: coreboot-v3/mainboard/amd/serengeti/dts
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/dts	2008-09-17 16:38:16 UTC (rev 866)
+++ coreboot-v3/mainboard/amd/serengeti/dts	2008-09-18 16:45:46 UTC (rev 867)
@@ -50,6 +50,9 @@
    		pci@2,0{
    		};
    	};
+		pci@18,1 {};
+		pci@18,2 {};
+		pci@18,3 {};
    	ioport@2e {
    		/config/("superio/winbond/w83627hf/dts");
    		com1enable = "1";

Modified: coreboot-v3/northbridge/amd/k8/domain.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/domain.c	2008-09-17 16:38:16 UTC (rev 866)
+++ coreboot-v3/northbridge/amd/k8/domain.c	2008-09-18 16:45:46 UTC (rev 867)
@@ -52,8 +52,6 @@

#define FX_DEVS 8
 extern struct device * __f0_dev[FX_DEVS];
-extern struct device * __f1_dev[FX_DEVS];
-void debug_fx_devs(void);
 void get_fx_devs(void);
 u32 f1_read_config32(unsigned int reg);
 void f1_write_config32(unsigned int reg, u32 value);
@@ -163,6 +161,7 @@
                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
                 IORESOURCE_MEM);
 #endif
+	printk(BIOS_DEBUG, "k8_pci_domain_read_resources done\n");
 }

static void k8_pci_domain_set_resources(struct device * dev)

Modified: coreboot-v3/northbridge/amd/k8/pci.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/pci.c	2008-09-17 16:38:16 UTC (rev 866)
+++ coreboot-v3/northbridge/amd/k8/pci.c	2008-09-18 16:45:46 UTC (rev 867)
@@ -48,9 +48,6 @@

#define FX_DEVS 8
 extern struct device * __f0_dev[FX_DEVS];
-extern struct device * __f1_dev[FX_DEVS];
-void debug_fx_devs(void);
-void get_fx_devs(void);
 u32 f1_read_config32(unsigned int reg);
 void f1_write_config32(unsigned int reg, u32 value);
 unsigned int amdk8_nodeid(struct device * dev);
@@ -66,7 +63,7 @@
                 unsigned max_bus;
                 unsigned min_bus;
    	unsigned max_devfn;
-
+	printk(BIOS_SPEW, "amdk8_scan_chain\n");
    	dev->link[link].cap = 0x80 + (link *0x20);
    	do {
    		link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
@@ -201,6 +198,7 @@

}

+	printk(BIOS_SPEW, "amdk8_scan_chain done\n");
    return max;
 }

@@ -244,7 +242,7 @@
         return max;
 }

-
+#warning document this unreadable function reg_useable
 static int reg_useable(unsigned reg, 
    struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link)
 {
@@ -252,9 +250,12 @@
    unsigned nodeid, link;
    int result;
    res = 0;
+#warning fix hard-coded 8 in for loop. 
    for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
    	struct device * dev;
    	dev = __f0_dev[nodeid];
+		if (! dev)
+			continue;
    	for(link = 0; !res && (link < 3); link++) {
    		res = probe_resource(dev, 0x100 + (reg | link));
    	}
@@ -379,9 +380,11 @@
    nodeid = amdk8_nodeid(dev);
    for(link = 0; link < dev->links; link++) {
    	if (dev->link[link].children) {
+			printk(BIOS_DEBUG, "amdk8_read_resources link %d\n", link);
    		amdk8_link_read_bases(dev, nodeid, link);
    	}
    }
+	printk(BIOS_DEBUG, "amdk8_read_resources done\n");
 }

static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid)