coreboot

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39687 discussions

How to enable lspci device heci/intel me to show up?
by J c 02 Dec '21

02 Dec '21

How to enable lspci device heci/intel me to show up? I have the me jumper set to normal Fdo jumper removed On retail bios i see the mei device but not on coreboot On intelmetool both shows mei device but why is it not initalized on the pci bus? I need it for enable graphics acceleration on hd4000 for osx. Thx Sent from my iPhone

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Gopdriver into coreboot
by Rao G 02 Dec '21

02 Dec '21

Hi All, Trying to figure out how the GOP driver is enabled/added in the coreboot tree. IntelGraphicsPeim.efi IntelGopDriver.efi Above 2 drivers part of FSP? Intel is providing DisCon tool to configure VBT, this tool is a replacement for BMP which is EOL Thanks for your time! Best Regards Ranga

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[coreboot - Support #324] (New) samsung r580
by coreboot＠fe80.eu 01 Dec '21

01 Dec '21

Issue #324 has been reported by kostya kuznetsov. ---------------------------------------- Support #324: samsung r580 https://ticket.coreboot.org/issues/324 * Author: kostya kuznetsov * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- model: np r580 js09 cpu: Intel(R) Core(TM) i3 CPU M 330 north bridge : Intel SLGZS (BD82HM55) gpu: GeForce GT 330M mother board: Bremen-M rev:1.3(100321)-8 lspci -tvnn -+-[0000:3f]-+-00.0 Intel Corporation Core Processor QuickPath Architecture Generic Non-core Registers [8086:2c62] | +-00.1 Intel Corporation Core Processor QuickPath Architecture System Address Decoder [8086:2d01] | +-02.0 Intel Corporation Core Processor QPI Link 0 [8086:2d10] | +-02.1 Intel Corporation 1st Generation Core i3/5/7 Processor QPI Physical 0 [8086:2d11] | +-02.2 Intel Corporation 1st Generation Core i3/5/7 Processor Reserved [8086:2d12] | \-02.3 Intel Corporation 1st Generation Core i3/5/7 Processor Reserved [8086:2d13] \-[0000:00]-+-00.0 Intel Corporation Core Processor DRAM Controller [8086:0044] +-01.0-[02]--+-00.0 NVIDIA Corporation GT216M [GeForce GT 330M] [10de:0a29] | \-00.1 NVIDIA Corporation GT216 HDMI Audio Controller [10de:0be2] +-1a.0 Intel Corporation 5 Series/3400 Series Chipset USB2 Enhanced Host Controller [8086:3b3c] +-1b.0 Intel Corporation 5 Series/3400 Series Chipset High Definition Audio [8086:3b56] +-1c.0-[03-04]----00.0 Qualcomm Atheros AR9285 Wireless Network Adapter (PCI-Express) [168c:002b] +-1c.2-[05-06]-- +-1c.3-[07-08]----00.0 Marvell Technology Group Ltd. Yukon Optima 88E8059 [PCIe Gigabit Ethernet Controller with AVB] [11ab:4381] +-1d.0 Intel Corporation 5 Series/3400 Series Chipset USB2 Enhanced Host Controller [8086:3b34] +-1e.0-[09]-- +-1f.0 Intel Corporation HM55 Chipset LPC Interface Controller [8086:3b09] +-1f.2 Intel Corporation 5 Series/3400 Series Chipset 4 port SATA AHCI Controller [8086:3b29] \-1f.3 Intel Corporation 5 Series/3400 Series Chipset SMBus Controller [8086:3b30] flashrom -p internal -V flashrom v1.2 on Linux 5.15.5-zen1-1-zen (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.6.4, GCC 9.3.0, little endian Command line (3 args): flashrom -p internal -V Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Laptop" Laptop detected via DMI. DMI string system-manufacturer: "SAMSUNG ELECTRONICS CO., LTD." DMI string system-product-name: "R580/R590 " DMI string system-version: "Not Applicable" DMI string baseboard-manufacturer: "SAMSUNG ELECTRONICS CO., LTD." DMI string baseboard-product-name: "R580/R590 " DMI string baseboard-version: "Not Applicable" Found chipset "Intel HM55" with PCI ID 8086:3b09. Enabling flash write... Root Complex Register Block address = 0xfed1c000 Error accessing ICH RCRB, 0x4000 bytes at 0x00000000fed1c000 /dev/mem mmap failed: Operation not permitted FAILED! FATAL ERROR! Error: Programmer initialization failed. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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i440bx PARALLEL_MP testing WAS: Re: Suggestion for deprecation: LEGACY_SMP_INIT & RESOURCE_ALLOCATOR_V3
by Branden Waldner 01 Dec '21

01 Dec '21

On 11/30/21, Keith Hui <buurin(a)gmail.com> wrote: > I suffered an unexpected exception after applying the patch train. > Serial log at the end of this email. I probably could leave out > bootblock/romstage/postcar, but it's here for completeness. Next: > bisect. I had a similar result testing on my P2B. I'm working on recovering it and I was planning on trying a build with log level spew on the P2-99 since it is easy for me to recover with the way I have it setup right now. Branden Waldner

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[coreboot - Bug #323] (New) thinkpad T60 expresscard support
by coreboot＠fe80.eu 30 Nov '21

30 Nov '21

Issue #323 has been reported by Michael Edelmann. ---------------------------------------- Bug #323: thinkpad T60 expresscard support https://ticket.coreboot.org/issues/323 * Author: Michael Edelmann * Status: New * Priority: Normal * Assignee: * Category: board support * Target version: ---------------------------------------- I was playing around with expresscard usb 3.0 adapters on a thinkpad T60 and noticed that coreboot breaks its functionality. i tested both the stock bios and coreboot revision b2e8bd83647f664260120fdfc7d07cba694dd89e, the logs listed under https://www.coreboot.org/Motherboard_Porting_Guide are included in the 'coreboot' and 'stock' directories. of course i had my card inserted when i took the logs lspci shows the card under the stock bios, it works fine. coreboot doesnt seem to do anything with it, its getting no power. the card i got, as seen in the attached image, has been known to work on GNU/Linux for other people out of the box, apparently not for coreboot. i'd be glad if coreboot supported expresscards for 2 additional USB ports, thanks for taking a look at it! ---Files-------------------------------- card.jpg (41.1 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Re: Suggestion for deprecation: LEGACY_SMP_INIT & RESOURCE_ALLOCATOR_V3
by Branden Waldner 30 Nov '21

30 Nov '21

I wasn't really sure that I wanted to comment on this, but seeing as how I have some of the affected boards I guess I should. Angel Pons wrote: > Besides AMD AGESA boards, the other boards that need to be updated are AOpen DXPL > Plus-U (a dual-socket server board that uses Netburst Xeons, no other board in the tree uses > the same chipset code) and various Asus P2B boards (which support Pentium 2/3 CPUs, these > boards are older than me). Even though I only know two people who still have some of these > boards (and they don't have the same boards), they're still supported because the code has > been maintained so far. I am one of the two with Asus P2B boards, with Keith Hui being the other. I've got a P2B and a P2-99 and I believe Keith Hui has a P2B-LS. So far there have not been very many changes and Keith Hui and others have worked on them, all I've done is test master and relevant patch sets every once in a while. I know I have not been uploading board_status results and I have not gotten around to fixing the variant set up for the P2-99 so I'm not uploading results that are uncertain about which board they are for. Not really relevant, but I think it is pretty neat to be running coreboot on boards older then some of the contributors. Mike Banon wrote: > I am often build-testing my boards (didn't notice a > https://review.coreboot.org/c/coreboot/+/59636 problem for a while, but only because I've been > re-using the previously built toolchains to save time). Also, I am actively tech-supporting all the > people who would like to build coreboot for AMD boards from this list, even right now I am in an > active message exchange with >10 people who are switching to these boards to run coreboot > on them - and any user may give back to the project one day. I actually have a few AMD boards and laptops that might be viable for porting to, but I've never looked in to it much because of the state support is in coreboot and the fact most of the hardware was actively being used. Arthur Heymans wrote: > The first one I'd like to deprecate is LEGACY_SMP_INIT. This also includes the codepath for > SMM_ASEG. This code is used to start APs and do some feature programming on each AP, but > also set up SMM. This has largely been superseded by PARALLEL_MP, which should be able > to cover all use cases of LEGACY_SMP_INIT, with little code changes. The reason for > deprecation is that having 2 codepaths to do the virtually the same increases maintenance > burden on the community a lot, while also being rather confusing. > > A few things are lacking in PARALLEL_MP init: - Support for !CONFIG_SMP on single core > systems. It's likely easy to extend PARALLEL_MP or write some code that just does CPU > detection on the BSP CPU. - Support smm in the legacy ASEG (0xa0000 - 0xb0000) region. A > POC showed that it's not that hard to do with PARALLEL_MP > https://review.coreboot.org/c/coreboot/+/58700 I didn't even know that was a problem until now. I doubt there is much I can do about it myself at this point in time, though I can try to look through it I guess. Branden Waldner

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Suggestion for deprecation: LEGACY_SMP_INIT & RESOURCE_ALLOCATOR_V3
by Arthur Heymans 29 Nov '21

29 Nov '21

Hi I would like to suggest to deprecate some legacy codepaths inside the coreboot tree and therefore make some newer ones mandatory. The first one I'd like to deprecate is LEGACY_SMP_INIT. This also includes the codepath for SMM_ASEG. This code is used to start APs and do some feature programming on each AP, but also set up SMM. This has largely been superseded by PARALLEL_MP, which should be able to cover all use cases of LEGACY_SMP_INIT, with little code changes. The reason for deprecation is that having 2 codepaths to do the virtually the same increases maintenance burden on the community a lot, while also being rather confusing. A few things are lacking in PARALLEL_MP init: - Support for !CONFIG_SMP on single core systems. It's likely easy to extend PARALLEL_MP or write some code that just does CPU detection on the BSP CPU. - Support smm in the legacy ASEG (0xa0000 - 0xb0000) region. A POC showed that it's not that hard to do with PARALLEL_MP https://review.coreboot.org/c/coreboot/+/58700 No platforms in the tree have any hardware limitations that would block migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase. The second codepath that I'd like to propose for deprecation is RESOURCE_ALLOCATOR_V3. V4 was introduced more than a year ago and with minor changes most platforms were able to work just fine with it. A major difference is that V3 uses just one continuous region below 4G to allocate all PCI memory BAR's. V4 uses all available space below 4G and if asked to, also above 4G too. This makes it important that SoC code properly reports all fixed resources. Currently only AGESA platforms have issues with it. On gerrit both attempts to fix AMD AGESA codebases to use V4 and compatibility modes inside the V4 allocator have been proposed, but both efforts seem stalled. See the (not yet merged) documentation https://review.coreboot.org/c/coreboot/+/43603 on it's details. It looks like properly reporting all fixed resources is the culprit. About the timeline of deprecations. Is deprecating non conforming platforms from the master branch after the 4.16 release in 6 months a reasonable proposal? The affected boards currently are: AMD_INAGUA AMD_OLIVEHILL AMD_PARMER AMD_SOUTHSTATION AOPEN_DXPLPLUSU AMD_PERSIMMON AMD_THATCHER AMD_UNIONSTATION ASROCK_E350M1 ASUS_A88XM_E ASROCK_IMB_A180 ASUS_AM1I_A ASUS_F2A85_M ASUS_F2A85_M_PRO ASUS_F2A85_M_LE ASUS_P2B_RAMDEBUG ASUS_P2B_LS ASUS_P2B_F ASUS_P2B_D ASUS_P2B_DS ASUS_P3B_F ASUS_P2B ODE_E20XX BIOSTAR_AM1ML BIOSTAR_A68N5200 ELMEX_PCM205400 ELMEX_PCM205401 GIZMOSPHERE_GIZMO2 GIZMOSPHERE_GIZMO HP_ABM HP_PAVILION_M6_1035DX JETWAY_NF81_T56N_LF LENOVO_G505S LIPPERT_FRONTRUNNER_AF LIPPERT_TOUCAN_AF MSI_MS7721 PCENGINES_APU1_ PCENGINES_APU2_ PCENGINES_APU3_ PCENGINES_APU4_ PCENGINES_APU5_ PCENGINES_APU1 PCENGINES_APU2 PCENGINES_APU3 PCENGINES_APU4 PCENGINES_APU5 sidenote: Qemu platforms support both LEGACY_SMP_INIT and PARALLEL_MP init so I did not list them here. Let me know your thoughts. Arthur

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DIP8 flash programming for development
by Pedro Erencia 28 Nov '21

28 Nov '21

Hi, I'm thinking about porting coreboot to a FM2A88X Extreme4+ board. This board has a DIP8 flash with a socket and I wondered what would be the best way to do an efficient development cycle. Ideally, I suppose that the best option would be to use a clip test and a CH341A, but all the clips that I found are SOIC/SOP. Should I buy a SOIC clip and an adapter from SOIC to DIP? I've seen those adapters, but I'm not sure if they will fit well in the mobo DIP8 socket. Aside from the mechanical question, I'd appreciate any advice about the safety of externally programming the board. I don't have the schematics and I wonder if there could be any risk of damaging the board. Cheers.

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Re: Suggestion for deprecation: LEGACY_SMP_INIT & RESOURCE_ALLOCATOR_V3
by Martin Roth 26 Nov '21

26 Nov '21

If someone wanted to work with one of the approved coreboot contractors or individual contributor to set up a fundraiser of some sort to raise money to do things like this, that'd be great. We've had a requests for things like this in the past, but it's not something that the coreboot project itself can really do. We don't want to pit one group of coreboot developers against another, and the coreboot project also doesn't deliver binaries or sign contracts for work, so coreboot can't make guarantees about deliverables. I'd be happy to help get a fundraiser set up if anyone is interested in doing the work, but it's going to have to go through an actual fundraising site, and of course we'd want to have a full written plan before starting anything. Martin Nov 25, 2021, 18:03 by k.emery.nbn(a)internode.on.net: > I'm happy to contribute financially. It just comes with the caveat that I need to know with some surety that I can finally have a working board at the end of it. > > On a side note is there any kind of crowd sourcing platform / escrow service for GPL projects? I know it's been talked about, and there have been attempts made. But as far as I can tell, nothing has ever prospered. > > >> My ballpark estimation is a total of less than 100hours of >> contributors' time to migrate AGESA platform codes to avoid >> deprecation. Shared between five people who know what they are doing, >> it is very much doable within a month. >> >> Kind regards, >> Kyösti Mälkki >> _______________________________________________ >> coreboot mailing list -- coreboot(a)coreboot.org >> To unsubscribe send an email to coreboot-leave(a)coreboot.org >> > _______________________________________________ > coreboot mailing list -- coreboot(a)coreboot.org > To unsubscribe send an email to coreboot-leave(a)coreboot.org >

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Question on flashrom 1.2
by Rao G 25 Nov '21

25 Nov '21

Hi Coreboot Team, Am trying flashrom 1.2 on W25R256JVEIQ NOR flash. Datasheet below https://www.mouser.ie/datasheet/2/949/Winbond_Electronics_Corporation_11012… Flashrom supports below winbond DEVID's but not W25R series? In Ubuntu /sys/class/mtd0 does not exist error is seen #define WINBOND_NEX_W25Q40_V 0x4013 /* W25Q40BV; W25Q40BL (2.3-3.6V) */ #define WINBOND_NEX_W25Q80_V 0x4014 /* W25Q80BV */ #define WINBOND_NEX_W25Q16_V 0x4015 /* W25Q16CV; W25Q16DV */ #define WINBOND_NEX_W25Q32_V 0x4016 /* W25Q32BV; W25Q32FV in SPI mode (default) */ #define WINBOND_NEX_W25Q64_V 0x4017 /* W25Q64BV, W25Q64CV; W25Q64FV in SPI mode (default) */ #define WINBOND_NEX_W25Q128_V 0x4018 /* W25Q128BV; W25Q128FV in SPI mode (default) */ #define WINBOND_NEX_W25Q256_V 0x4019 /* W25Q256FV or W25Q256JV_Q (QE=1) */ #define WINBOND_NEX_W25Q512JV 0x4020 /* W25Q512JV */ #define WINBOND_NEX_W25Q20_W 0x5012 /* W25Q20BW */ #define WINBOND_NEX_W25Q40BW 0x5013 /* W25Q40BW */ #define WINBOND_NEX_W25Q80BW 0x5014 /* W25Q80BW */ #define WINBOND_NEX_W25Q40EW 0x6013 /* W25Q40EW */ #define WINBOND_NEX_W25Q80EW 0x6014 /* W25Q80EW */ #define WINBOND_NEX_W25Q16_W 0x6015 /* W25Q16DW */ #define WINBOND_NEX_W25Q32_W 0x6016 /* W25Q32DW; W25Q32FV in QPI mode */ #define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ #define WINBOND_NEX_W25Q128_W 0x6018 /* W25Q128FW; W25Q128FV in QPI mode */ #define WINBOND_NEX_W25Q256_W 0x6019 /* W25Q256JW */ #define WINBOND_NEX_W25Q128_V_M 0x7018 /* W25Q128JVSM */ #define WINBOND_NEX_W25Q256JV_M 0x7019 /* W25Q256JV_M (QE=0) */ #define WINBOND_NEX_W25Q32JW_M 0x8016 /* W25Q32JW...M */ #define WINBOND_NEX_W25Q64JW_M 0x8017 /* W25Q64JW...M */ #define WINBOND_NEX_W25Q128_DTR 0x8018 /* W25Q128JW_DTR */ #define WINBOND_NEX_W25Q256_DTR 0x8019 /* W25Q256JW_DTR aka W25Q256256JW-IM */ Is anyone aware whether the specific DEVID not supporting causes /sys/class/mtd0 does not exist? Thanks for your time! Best Regards Rao

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