coreboot

coreboot@coreboot.org

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39654 discussions

search_isolinux usb
by Geert Stappers 08 Aug '22

08 Aug '22

Hello coreboot developers, Here a coreboot user who wishes to boot from an USB-memory-stick. That is in addition to regular boot from internal storage device. The computer I'm talking about is a Lenovo Thinkpad X230 which does have coreboot installed, it is what I have bought. Payload is grub. An .iso is fetched from Internet and `dd` to USB-memory-stick. The USB-thumbdrive is then inserted in the X230, on the left side, in the USB-slot closest to user[1]. Upon power-on is a grub menu shown[2]. Default menu entry has description "Load operating system", beneat is `search_grub ahci` and does indeed load and start Linux. (in ohter words: payload came alive) However the other boot menu entries[3] don't work. It is the reason why I'm seeking your advice. When I active menu entry 'Search ISOLINUX menu (USB)', which has grub command 'search_isolinux usb', screen goes shortly black and then the main grub menu re-appears. As if the coreboot payload grub wants to tell "nothing found". For the other boot menu entries I also get "nothing found". What to do to make coreboot grub accepting USB image? Groeten Geert Stappers [1] Other USB-slots have also been tried. Only with the "front-left-USB-slot" do I see a blinking activity LED of the USB-memory-stick. [2] Other power-up-messages might have been printed, but the quick appearance of the grub menu overwrites then. [3] "Poweroff" and "Reboot" are not **boot** menu entries. -- Silence is hard to parse

3 2

configure: error: qemu, coreboot and loongson ports need unifont
by Geert Stappers 08 Aug '22

08 Aug '22

Hello coreboot archive, After a succesfull build of the default payload, I tried to build the grub payload and got configure: error: qemu, coreboot and loongson ports need unifont make[1]: *** [Makefile:34: grub2/build/config.h] Error 1 make: *** [payloads/external/Makefile.inc:224: grub2] Error 2 In https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/IVK… is adviced to do sudo apt install -y autoconf automake gettext autopoint pkg-config grub-common libfreetype6-dev unifont but no report on how succesfull that was. Now I report: Yes, those extra packages on the host got me a succesfull of the grub payload. Groeten Geert Stappers -- Silence is hard to parse

1 0

Image size and cpu-flash addresses.
by Pedro Erencia 07 Aug '22

07 Aug '22

Hi everyone, I was going to try coreboot on an ASROCK FM2A88X Extreme4+ ( https://www.asrock.com/mb/AMD/FM2A88X%20Extreme4+/) with the configuration of the supported ASUS A88XM-E ( https://doc.coreboot.org/mainboard/asus/a88xm-e.html) which has the same chipset (A88X Bolton). The fact is that, at this moment, I only have a 16 MiB flash, while the image is 8 MiB. As the chipset claims that it “Supports a maximum SPI ROM size of 16MB” I think there should be no problem, but I wonder how I have to burn the image. That led me to the question of how the translation between CPU and flash addresses are done. For supporting various ROM sizes, I guess the controller should somehow know the size of the ROM, but I don't see anywhere where that could be specified. The only thing I found is this stack overflow question ( https://stackoverflow.com/questions/60200796/how-does-processor-read-bios-f…). There, flash descriptors and some straps are mentioned to provide the ROM size, but none of those methods are mentioned on the Bolton Datasheet. So I have two questions here, 1. How should I burn the 8 MiB image on the 16 MiB flash? 2. Out of curiosity, how is the cpu-flash address translation done?

3 2

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 05 Aug '22

05 Aug '22

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 4 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 4 of 4 defect(s) ** CID 1490983: Control flow issues (DEADCODE) /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 1210 in edp_ctrl_calc_tu() ________________________________________________________________________________________________________ *** CID 1490983: Control flow issues (DEADCODE) /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 1210 in edp_ctrl_calc_tu() 1204 temp_fp = LCLK_FAST_SKEW_fp * tu->lwidth; 1205 temp = DIV_ROUND_UP(temp_fp, f); 1206 temp_fp = ((tu->bpp * f / 8) / (tu->nlanes * tu->original_ratio_fp)) * f * temp; 1207 temp = temp_fp / f; 1208 1209 if (async_en) >>> CID 1490983: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "tu->delay_start_link += (in...". 1210 tu->delay_start_link += (int)temp; 1211 tu->delay_start_time_fp = (tu->delay_start_link * f) / tu->lclk; 1212 1213 /* OUTPUTS */ 1214 tu_table->valid_boundary_link = tu->valid_boundary_link; 1215 tu_table->delay_start_link = tu->delay_start_link; ** CID 1490982: (RESOURCE_LEAK) /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 1235 in edp_ctrl_calc_tu() /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 1235 in edp_ctrl_calc_tu() /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 1235 in edp_ctrl_calc_tu() /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 1235 in edp_ctrl_calc_tu() ________________________________________________________________________________________________________ *** CID 1490982: (RESOURCE_LEAK) /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 1235 in edp_ctrl_calc_tu() 1229 tu_table->valid_lower_boundary_link); 1230 printk(BIOS_INFO, "TU: upper_boundary_count: %d\n", 1231 tu_table->upper_boundary_count); 1232 printk(BIOS_INFO, "TU: lower_boundary_count: %d\n", 1233 tu_table->lower_boundary_count); 1234 printk(BIOS_INFO, "TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1); >>> CID 1490982: (RESOURCE_LEAK) >>> Variable "tu" going out of scope leaks the storage it points to. 1235 } 1236 1237 static void edp_ctrl_config_TU(struct edp_ctrl *ctrl, struct edid *edid) 1238 { 1239 struct edp_ctrl_tu tu_config; 1240 /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 1235 in edp_ctrl_calc_tu() 1229 tu_table->valid_lower_boundary_link); 1230 printk(BIOS_INFO, "TU: upper_boundary_count: %d\n", 1231 tu_table->upper_boundary_count); 1232 printk(BIOS_INFO, "TU: lower_boundary_count: %d\n", 1233 tu_table->lower_boundary_count); 1234 printk(BIOS_INFO, "TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1); >>> CID 1490982: (RESOURCE_LEAK) >>> Variable "tu" going out of scope leaks the storage it points to. 1235 } 1236 1237 static void edp_ctrl_config_TU(struct edp_ctrl *ctrl, struct edid *edid) 1238 { 1239 struct edp_ctrl_tu tu_config; 1240 /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 1235 in edp_ctrl_calc_tu() 1229 tu_table->valid_lower_boundary_link); 1230 printk(BIOS_INFO, "TU: upper_boundary_count: %d\n", 1231 tu_table->upper_boundary_count); 1232 printk(BIOS_INFO, "TU: lower_boundary_count: %d\n", 1233 tu_table->lower_boundary_count); 1234 printk(BIOS_INFO, "TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1); >>> CID 1490982: (RESOURCE_LEAK) >>> Variable "tu" going out of scope leaks the storage it points to. 1235 } 1236 1237 static void edp_ctrl_config_TU(struct edp_ctrl *ctrl, struct edid *edid) 1238 { 1239 struct edp_ctrl_tu tu_config; 1240 /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 1235 in edp_ctrl_calc_tu() 1229 tu_table->valid_lower_boundary_link); 1230 printk(BIOS_INFO, "TU: upper_boundary_count: %d\n", 1231 tu_table->upper_boundary_count); 1232 printk(BIOS_INFO, "TU: lower_boundary_count: %d\n", 1233 tu_table->lower_boundary_count); 1234 printk(BIOS_INFO, "TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1); >>> CID 1490982: (RESOURCE_LEAK) >>> Variable "tu" going out of scope leaks the storage it points to. 1235 } 1236 1237 static void edp_ctrl_config_TU(struct edp_ctrl *ctrl, struct edid *edid) 1238 { 1239 struct edp_ctrl_tu tu_config; 1240 ** CID 1490981: Integer handling issues (DIVIDE_BY_ZERO) /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 936 in edp_ctrl_pixel_clock_dividers() ________________________________________________________________________________________________________ *** CID 1490981: Integer handling issues (DIVIDE_BY_ZERO) /src/soc/qualcomm/sc7280/display/edp_ctrl.c: 936 in edp_ctrl_pixel_clock_dividers() 930 pixel_div = 2; 931 else if (rate == DP_LINK_BW_5_4) 932 pixel_div = 4; 933 else 934 printk(BIOS_ERR, "Invalid pixel mux divider\n"); 935 >>> CID 1490981: Integer handling issues (DIVIDE_BY_ZERO) >>> In expression "ctrl->link_rate_khz * 10U / pixel_div", division by expression "pixel_div" which may be zero has undefined behavior. 936 dispcc_input_rate = (ctrl->link_rate_khz * 10) / pixel_div; 937 938 rational_best_approximation(dispcc_input_rate, stream_rate_khz, 939 (unsigned long)(1 << 16) - 1, 940 (unsigned long)(1 << 16) - 1, &den, &num); 941 *pixel_m = num; ** CID 1490980: (TAINTED_SCALAR) ________________________________________________________________________________________________________ *** CID 1490980: (TAINTED_SCALAR) /3rdparty/vboot/firmware/2lib/2load_kernel.c: 629 in vb2api_load_kernel() 623 if (AllocAndReadGptData(disk_info->handle, &gpt)) { 624 VB2_DEBUG("Unable to read GPT data\n"); 625 goto gpt_done; 626 } 627 628 /* Initialize GPT library */ >>> CID 1490980: (TAINTED_SCALAR) >>> Passing tainted expression "*gpt.primary_header" to "GptInit", which uses it as a loop boundary. 629 if (GptInit(&gpt)) { 630 VB2_DEBUG("Error parsing GPT\n"); 631 goto gpt_done; 632 } 633 634 /* Loop over candidate kernel partitions */ /3rdparty/vboot/firmware/2lib/2load_kernel.c: 629 in vb2api_load_kernel() 623 if (AllocAndReadGptData(disk_info->handle, &gpt)) { 624 VB2_DEBUG("Unable to read GPT data\n"); 625 goto gpt_done; 626 } 627 628 /* Initialize GPT library */ >>> CID 1490980: (TAINTED_SCALAR) >>> Passing tainted expression "*gpt.secondary_header" to "GptInit", which uses it as a loop boundary. 629 if (GptInit(&gpt)) { 630 VB2_DEBUG("Error parsing GPT\n"); 631 goto gpt_done; 632 } 633 634 /* Loop over candidate kernel partitions */ ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Servers?
by Jeremy Hansen 03 Aug '22

03 Aug '22

I’ve looked at the list of hardware vendors. I see System76 listed but when I asked System76, they claim it’s not supported. “Support” I understand, but does it work? Maybe using their System76 firmware? Any other server vendors I should consider? I know Purism offers servers as well. Anyone else? Thank you -jeremy

4 6

Custom coreboot installer and license
by Felix Freeman 28 Jul '22

28 Jul '22

Hello people, This is a question and kind-of an announcement. I'm just a few days ahead of the official opening of an online store that will sell corebooted laptops in Chile. For this purpose I've created a custom coreboot installer, and, since it's useful to me, I thought it could be useful for other people and uploaded it to the tubes. Code is here: https://git.hacktivista.org/hackware-boot This software is not a fork of coreboot, but an automated compiler/installer of coreboot that of course uses its tools. These are not shipped with it, but downloaded from git or the Debian repos. In case you're wondering what's different from Skulls or osboot: It includes several security enhacements through the combination of a custom GRUB config and the usage of a custom tool called hwbtool. It also ships all available payloads that libgfxinit supports by default. I built it because I needed to automate the installation for my store's laptops. Here the difficult part: I want to publish it (it's currently published indeed) under license that's incompatible with the GPL. The question is, is this legal? Also distributing the result of such combination? Examples of such usage can be found here: https://git.sr.ht/~hacktivista/hackware-boot/tree/main/item/x230t/flash_spi… https://git.sr.ht/~hacktivista/hackware-boot/tree/main/item/hwbtool#L167 As far as I understand I'm just using a software in a separate program, not linking nor intending to distribute derivatives of coreboot project programs under other license. But I thought it's better to ask. Please refrain from asking out of topic questions regarding the software or the license on this thread. I know it might be a hot topic for some people and will happily answer via private email or even on a completely new thread here on this same list. Thanks a lot, Felix Freeman

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Re: ASUS P8ZZ7-V i7-3770 >16GB RAM: SPD CRC failed
by Kevin Keijzer 28 Jul '22

28 Jul '22

I have this exact same board (P8Z77-V) with the exact same CPU (i7-3770), the exact same DIMM's (4x 8GB CMZ16GX3M2A1600C9), and the same coreboot version (4.17), and it's working fine for me for months now. When I leave CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS to its default of n, the memory is clocked at 1333MHz (as the XMP profile says you may only use one DIMM per channel), but when I set CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS=y, it's clocked at 1600MHz. In both cases the system works perfectly well with 32GB RAM. (I tested 1333MHz in the beginning, and later switched to 1600MHz.) So I don't understand why it wouldn't work with another identical setup. The logs show that the system reboots shortly after "SPD probe channel0, slot1". It seems to fail halfway during the probe, likely resulting in "Stored timings CRC16 mismatch." during the next try. I've never tested the vendor BIOS on my board, so I have no idea if it should work there or not. So why does the board reset halfway during an SPD probe? Could this be a faulty memory controller or something we're overlooking? -- With kind regards, Kevin Keijzer

1 0

camelback mountain CRB graphics support + UefiPayload
by Moorthi M.s 28 Jul '22

28 Jul '22

Hi, We are developing coreboot along with UefiPayload for camelback mountain crb. The processor doesn't have the inbuilt graphics support. Add-on graphics card is used in the CRB. Graphics is initialised and working with SeaBios as payload. But when we configured to use UefiPayload, shell and boot options are not visible in graphics display. A cursor is blinking in the display and the shell is visible in the UART console. Is there any configuration required for UefiPayload with respect to graphics? Thanks & regards, Moorthi

1 0

Re: ASUS P8ZZ7-V i7-3770 >16GB RAM: SPD CRC failed
by Kevin Keijzer 27 Jul '22

27 Jul '22

1 0

[coreboot - Bug #332] (Resolved) I selected payload Tianocore Upstream (not UEFIPayload) but its still using MrChromebox UEFIPayload files?
by Sean Rhodes 26 Jul '22

26 Jul '22

Issue #332 has been updated by Sean Rhodes. Status changed from Response Needed to Resolved The old makefile used to add upstream as a remote, which is why it looks like it's using MrChromebox. It does, and always has, built from the correct repo. ---------------------------------------- Bug #332: I selected payload Tianocore Upstream (not UEFIPayload) but its still using MrChromebox UEFIPayload files? https://ticket.coreboot.org/issues/332#change-1052 * Author: xinhua wang * Status: Resolved * Priority: Normal * Start date: 2021-12-30 ---------------------------------------- make V=1 -d Cloning Tianocore from Git Reaping winning child 0x559abd8daf20 PID 142498 git clone --branch uefipayload_202107 https://github.com/mrchromebox/edk2 /mnt/cb-trying-upstream/coreboot/payloads/external/tianocore/tianocore; \ cd /mnt/cb-trying-upstream/coreboot/payloads/external/tianocore/tianocore; \ git remote add upstream https://github.com/tianocore/edk2 Live child 0x559abd8daf20 (/mnt/cb-trying-upstream/coreboot/payloads/external/tianocore/tianocore) PID 142499 Cloning into '/mnt/cb-trying-upstream/coreboot/payloads/external any ideas, thx -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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