coreboot

coreboot@coreboot.org

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39654 discussions

Comment faire ? How to ?
by s.ginape＠tutanota.com 22 Aug '22

22 Aug '22

Bonjour, J'ai en ma possession un mw-gmlk-2_5g4l et je voudrais le passer sous coreboot. Comment puis flasher le bios? Y-a-t-il une image à mettre sur une clé USB? Cordialement. Hello I have in my possession a mw-gmlk-2_5g4l and I would like to pass it under coreboot. How to flash the bios? Is there an image to put on a USB flash drive? Kind regards.

1 0

Issue tracker version update / disabling of login methods
by Felix Singer 18 Aug '22

18 Aug '22

Hi all, the Redmine developers released version 5.0 some months ago and updating to this version will have some effects on us. So, I would like to open a thread to discuss these issues with you and how we deal with that situation. Currently, we are on the 4.2 branch and it still gets security and bug fixes, but I can't tell at which point they will stop supporting it. We enabled the login over OpenID, which is implemented natively and not integrated over a plugin. With version 5.0, support for that was removed. I assume this is due to that the implementation is based on an older OpenID standard and there are not many users of it anymore (TM). The newer standard seems to be called "OpenID Connect", but it's not supported by Redmine. Also, we are using a plugin which allows the login over a Google account. The compatibility of that plugin breaks with version 5.0. The problem is that we have users for both and with version 5.0 they won't be able to use these methods anymore. However, I have an idea for a solution. I took a look at the Redmine database and I played around with the Google login method. My tests showed that it creates a normal user account, as it is done with the registration, just with the little difference that no password is set disabling the login over password. These accounts also have an user name and an email address. As soon as I set a password, I was able to login using the user name. So, my idea is that we just go with these changes and affected users use the functionality to reset their password, which means they will have a "normal" user account then. In preparation to that version update, we should disable these login methods so that no new users will make use of them. Other ideas? What's your opinion? // Felix

3 4

Intel sandybridge northbridge with ibexpeak southbridge?
by Hal Martin 18 Aug '22

18 Aug '22

Hello, I have a platform (Advantech NAMB-3250MB, used in some Riverbed appliances) which uses Sandy/Ivy Bridge CPUs, but has a DH89xxCC southbridge which according to ifdtool is Ibex Peak. [3] The ME firmware version from the vendor firmware is 6.0.50.1244 which also corresponds to Ibex Peak (Series 5) and not Cougar Point (Series 6). [1] I did not know it was possible to pair a Series 5 chipset with Sandy/Ivy Bridge, since the DH89xxCC only supports DMI 1 (intel-communications-chipset-89xx-series-datasheet.pdf page 5) and Sandy/Ivy Bridge support DMI 2.0 [2] It would appear that using northbridge/intel/sandybridge with southbridge/intel/ibexpeak in coreboot is not supported: /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/romstage/northbridge/intel/sandybridge/early_dmi.o: in function `early_init_dmi': /opt/coreboot/src/northbridge/intel/sandybridge/early_dmi.c:175: undefined reference to `early_pch_init_native_dmi_pre' /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /opt/coreboot/src/northbridge/intel/sandybridge/early_dmi.c:215: undefined reference to `early_pch_init_native_dmi_post' /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/romstage/northbridge/intel/sandybridge/raminit.o: in function `init_dram_ddr3': /opt/coreboot/src/northbridge/intel/sandybridge/raminit.c:322: undefined reference to `early_pch_init_native' src/arch/x86/Makefile.inc:185: recipe for target 'build/cbfs/fallback/romstage.debug' failed make: *** [build/cbfs/fallback/romstage.debug] Error 1 There is no early_pch_init_native_* in src/southbridge/intel/ibexpeak Is it safe to assume that IronLake northbridge is not applicable to Sandy/Ivy Bridge CPUs? In which case, I guess the only way this platform could ever be supported is if the missing early_pch_init_native_* functions are implemented for IbexPeak? Kind regards, Hal Martin [1] https://en.wikichip.org/wiki/intel/management_engine [2] https://www.intel.com/content/www/us/en/products/platforms/details/crystal-… [3] ./ifdtool dump.bin PCH Revision: 5 series Ibex Peak FLMAP0: 0x02040002 NR: 2 FRBA: 0x40 NC: 1 FCBA: 0x20 FLMAP1: 0x10100206 ISL: 0x10 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00000120 PSL: 0x0001 FMSBA: 0x200 FLUMAP1: 0x000002ef Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000ef0 ME VSCC table: JID0: 0x004b25bf SPI Component Vendor ID: 0xbf SPI Component Device ID 0: 0x25 SPI Component Device ID 1: 0x4b VSCC0: 0x20092009 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: Yes Lower Write Granularity: 1 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: Yes Upper Write Granularity: 1 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x07ff0400 Flash Region 1 (BIOS): 00400000 - 007fffff FLREG2: 0x03ff0001 Flash Region 2 (Intel ME): 00001000 - 003fffff FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x0010001c Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 20MHz Write/Erase Clock Frequency: 20MHz Fast Read Clock Frequency: 20MHz Fast Read Support: supported Read Clock Frequency: 20MHz Component 2 Density: 4MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0 : 0x00205602 PCHSTRP1 : 0x0000010f PCHSTRP2 : 0x90000000 PCHSTRP3 : 0x00000000 PCHSTRP4 : 0x00c8e000 PCHSTRP5 : 0x00000000 PCHSTRP6 : 0x00000000 PCHSTRP7 : 0x00000000 PCHSTRP8 : 0x00000000 PCHSTRP9 : 0x00000000 PCHSTRP10 : 0x00010044 PCHSTRP11 : 0x99000097 PCHSTRP12 : 0x00000000 PCHSTRP13 : 0x00000000 PCHSTRP14 : 0x00000000 PCHSTRP15 : 0x0000000e AltMeDisable bit is not set Found Master Section FLMSTR1: 0xffff0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0xffff0000 (Intel ME) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR3: 0xffff0118 (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 Found Processor Strap Section ????: 0x00000000 ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff

2 1

DDR4 detection issue in the Memory Down approach on the intel Denverton board
by Somanna Ankaiah 18 Aug '22

18 Aug '22

Greetings . We are working on intel c508 intel denverton board . It has a soldered 4GB DDR4 connected to Channel 0 , Dimm 0 . Below are the changes made : 1. We are using harcuvar board as a reference . I have selected * Enable Memory down option in menu config 2. Added spd values file in src/mainboard/intel/harcuvar/spd/spd_filename.hex 3. spd.bn getting generated in CBFS FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 43844 none cpu_microcode_blob.bin 0xac40 microcode 11264 none fallback/ramstage 0xd8c0 stage 71762 none config 0x1f180 raw 1353 none revision 0x1f740 raw 694 none spd.bin 0x1fa40 spd 512 none fallback/dsdt.aml 0x1fc80 raw 7791 none fallback/postcar 0x21b40 stage 23808 none fallback/payload 0x27880 simple elf 656810 none (empty) 0xc7e80 null 6651672 none fspt.bin 0x71fdc0 fsp 4096 none (empty) 0x720e00 null 3992 none fspm.bin 0x721dc0 fsp 589824 none (empty) 0x7b1e00 null 3992 none fsps.bin 0x7b2dc0 fsp 102400 none (empty) 0x7cbe00 null 114584 none bootblock 0x7e7dc0 bootblock 32768 none COREBOOT-4.13 PrivateBuild:saurabh Thu Jun 30 18:39:22 IST 2022 bootblock starting FSP TempRamInit successful... Timestamp - end of bootblock: 47603172 FMAP: Found "FLASH" version 1.1 at 0x810000. FMAP: base = 0xff000000 size = 0x1000000 #areas = 4 FMAP: area COREBOOT found @ 810200 (8322560 bytes) CBFS DEBUG: Looking for next file @0x0... CBFS DEBUG: Found CBFS header @0x0 (type 2, attr +0x0, data +0x38, length 0x20) CBFS DEBUG: File name: 'cbfs master header' CBFS DEBUG: Looking for next file @0x58... CBFS DEBUG: Found CBFS header @0x80 (type 16, attr +0x0, data +0x64, length 0xab44) CBFS DEBUG: File name: 'fallback/romstage' CBFS: Found 'fallback/romstage' @0x80 size 0xab44 Timestamp - starting to load romstage: 136192248 Timestamp - finished loading romstage: 143418624 BS: bootblock times (exec / console): total (unknown) / 74 ms 4. Tried giving 512 values CONFIG_DIMM_SPD_SIZE=512 5. Using 4GB DDR4 module. MT40A512M16LY-062E IT:E We are using Fitc tool to generate full FW image, getting below error and got stuck after loading the build ====================================================================================== COREBOOT-4.13 PrivateBuild:saurabh Thu Jun 30 18:39:22 IST 2022 romstage starting FSP TempRamInit was successful... Board ID: 0x52. GPIO table: 0xff81a144, entry num: 0x1! Changing GpioPad PID: c2 Offset: 0x400 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! TCO base address set to 0x400! FMAP: area COREBOOT found @ 810200 (8322560 bytes) CBFS DEBUG: Looking for next file @0x0... CBFS DEBUG: Found CBFS header @0x0 (type 2, attr +0x0, data +0x38, length 0x20) CBFS DEBUG: File name: 'cbfs master header' CBFS DEBUG: Looking for next file @0x58... CBFS DEBUG: Found CBFS header @0x80 (type 16, attr +0x0, data +0x64, length 0xab44) CBFS DEBUG: File name: 'fallback/romstage' CBFS DEBUG: Looking for next file @0xac28... CBFS DEBUG: Found CBFS header @0xac40 (type 83, attr +0x38, data +0x50, length 0x2c00) CBFS DEBUG: File name: 'cpu_microcode_blob.bin' CBFS DEBUG: Looking for next file @0xd890... CBFS DEBUG: Found CBFS header @0xd8c0 (type 16, attr +0x0, data +0x38, length 0x11853) CBFS DEBUG: File name: 'fallback/ramstage' CBFS DEBUG: Looking for next file @0x1f14b... CBFS DEBUG: Found CBFS header @0x1f180 (type 80, attr +0x28, data +0x38, length 0x549) CBFS DEBUG: File name: 'config' CBFS DEBUG: Looking for next file @0x1f701... CBFS DEBUG: Found CBFS header @0x1f740 (type 80, attr +0x28, data +0x38, length 0x2b6) CBFS DEBUG: File name: 'revision' CBFS DEBUG: Looking for next file @0x1fa2e... CBFS DEBUG: Found CBFS header @0x1fa40 (type 171, attr +0x28, data +0x38, length 0x200) CBFS DEBUG: File name: 'spd.bin' CBFS DEBUG: Looking for next file @0x1fc78... CBFS DEBUG: Found CBFS header @0x1fc80 (type 80, attr +0x38, data +0x48, length 0x1e6f) CBFS DEBUG: File name: 'fallback/dsdt.aml' CBFS DEBUG: Looking for next file @0x21b37... CBFS DEBUG: Found CBFS header @0x21b40 (type 16, attr +0x0, data +0x38, length 0x5d00) CBFS DEBUG: File name: 'fallback/postcar' CBFS DEBUG: Looking for next file @0x27878... CBFS DEBUG: Found CBFS header @0x27880 (type 32, attr +0x0, data +0x38, length 0xa05aa) CBFS DEBUG: File name: 'fallback/payload' CBFS DEBUG: Looking for next file @0xc7e62... CBFS DEBUG: Found CBFS header @0xc7e80 (type -1, attr +0x0, data +0x28, length 0x657f18) CBFS DEBUG: Looking for next file @0x71fdc0... CBFS DEBUG: Found CBFS header @0x71fdc0 (type 96, attr +0x28, data +0x40, length 0x1000) CBFS DEBUG: File name: 'fspt.bin' CBFS DEBUG: Looking for next file @0x720e00... CBFS DEBUG: Found CBFS header @0x720e00 (type -1, attr +0x0, data +0x28, length 0xf98) CBFS DEBUG: Looking for next file @0x721dc0... CBFS DEBUG: Found CBFS header @0x721dc0 (type 96, attr +0x28, data +0x40, length 0x90000) CBFS DEBUG: File name: 'fspm.bin' CBFS: Found 'fspm.bin' @0x721dc0 size 0x90000 Spec version: v2.0 Revision: 0.0.1, Build Number 18 Type: release/test image ID: DNV-FSP0, base 0xfff32000 + 0x90000 Config region 0x18c + 0x200 Memory init offset 0x450 Timestamp - before RAM initialization: 2111263908 FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' bootmode is set to: 0 Relaxing the Security Config for SPI. mupd->FspmConfig.RelaxSecConfig FMAP: area COREBOOT found @ 810200 (8322560 bytes) CBFS DEBUG: Looking for next file @0x0... CBFS DEBUG: Found CBFS header @0x0 (type 2, attr +0x0, data +0x38, length 0x20) CBFS DEBUG: File name: 'cbfs master header' CBFS DEBUG: Looking for next file @0x58... CBFS DEBUG: Found CBFS header @0x80 (type 16, attr +0x0, data +0x64, length 0xab44) CBFS DEBUG: File name: 'fallback/romstage' CBFS DEBUG: Looking for next file @0xac28... CBFS DEBUG: Found CBFS header @0xac40 (type 83, attr +0x38, data +0x50, length 0x2c00) CBFS DEBUG: File name: 'cpu_microcode_blob.bin' CBFS DEBUG: Looking for next file @0xd890... CBFS DEBUG: Found CBFS header @0xd8c0 (type 16, attr +0x0, data +0x38, length 0x11853) CBFS DEBUG: File name: 'fallback/ramstage' CBFS DEBUG: Looking for next file @0x1f14b... CBFS DEBUG: Found CBFS header @0x1f180 (type 80, attr +0x28, data +0x38, length 0x549) CBFS DEBUG: File name: 'config' CBFS DEBUG: Looking for next file @0x1f701... CBFS DEBUG: Found CBFS header @0x1f740 (type 80, attr +0x28, data +0x38, length 0x2b6) CBFS DEBUG: File name: 'revision' CBFS DEBUG: Looking for next file @0x1fa2e... CBFS DEBUG: Found CBFS header @0x1fa40 (type 171, attr +0x28, data +0x38, length 0x200) CBFS DEBUG: File name: 'spd.bin' CBFS: Found 'spd.bin' @0x1fa40 size 0x200 SPD spd_data[i] 23 SPD spd_data[i] 11 SPD spd_data[i] c SPD spd_data[i] 3 SPD spd_data[i] 56 SPD spd_data[i] 21 SPD spd_data[i] 0 SPD spd_data[i] 8 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 3 SPD spd_data[i] 2 SPD spd_data[i] b SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 8 SPD spd_data[i] d SPD spd_data[i] fc SPD spd_data[i] ab SPD spd_data[i] ae SPD spd_data[i] 0 SPD spd_data[i] 78 SPD spd_data[i] 78 SPD spd_data[i] 78 SPD spd_data[i] 11 SPD spd_data[i] 8 SPD spd_data[i] 80 SPD spd_data[i] f0 SPD spd_data[i] a SPD spd_data[i] 20 SPD spd_data[i] 8 SPD spd_data[i] 0 SPD spd_data[i] 5 SPD spd_data[i] 0 SPD spd_data[i] f0 SPD spd_data[i] 2b SPD spd_data[i] 34 SPD spd_data[i] 2b SPD spd_data[i] 0 SPD spd_data[i] 78 SPD spd_data[i] 0 SPD spd_data[i] 14 SPD spd_data[i] 3c SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] c SPD spd_data[i] 2b SPD spd_data[i] 2d SPD spd_data[i] 4 SPD spd_data[i] 16 SPD spd_data[i] 35 SPD spd_data[i] 23 SPD spd_data[i] d SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 2c SPD spd_data[i] b SPD spd_data[i] 3 SPD spd_data[i] 24 SPD spd_data[i] 35 SPD spd_data[i] c SPD spd_data[i] 3 SPD spd_data[i] 2d SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] ec SPD spd_data[i] 9c SPD spd_data[i] b4 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] e7 SPD spd_data[i] c1 SPD spd_data[i] a9 SPD spd_data[i] 4d SPD spd_data[i] f SPD spd_data[i] 11 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 38 SPD spd_data[i] 41 SPD spd_data[i] 54 SPD spd_data[i] 46 SPD spd_data[i] 35 SPD spd_data[i] 31 SPD spd_data[i] 32 SPD spd_data[i] 36 SPD spd_data[i] 34 SPD spd_data[i] 48 SPD spd_data[i] 5a SPD spd_data[i] 2d SPD spd_data[i] 32 SPD spd_data[i] 47 SPD spd_data[i] 31 SPD spd_data[i] 41 SPD spd_data[i] 32 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 32 SPD spd_data[i] 80 SPD spd_data[i] 2c SPD spd_data[i] 41 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 Memory Down function is enabled! 0x0000000000000d0a: IA32_MTRRCAP: SMRR, WC, FIX, 10 variable MTRRs 0x0000000000000800: IA32_MTRR_DEF_TYPE: E, UC 0x0000000000000000: IA32_MTRR_FIX64K_00000 0x00000000 - 0x0007ffff: UC 0x0000000000000000: IA32_MTRR_FIX16K_80000 0x00080000 - 0x0009ffff: UC 0x0000000000000000: IA32_MTRR_FIX16K_A0000 0x000a0000 - 0x000bffff: UC 0x0000000000000000: IA32_MTRR_FIX4K_C0000 0x000c0000 - 0x000c7fff: UC 0x0000000000000000: IA32_MTRR_FIX4K_C8000 0x000c8000 - 0x000cffff: UC 0x0000000000000000: IA32_MTRR_FIX4K_D0000 0x000d0000 - 0x000d7fff: UC 0x0000000000000000: IA32_MTRR_FIX4K_D8000 0x000d8000 - 0x000dffff: UC 0x0000000000000000: IA32_MTRR_FIX4K_E0000 0x000e0000 - 0x000e7fff: UC 0x0000000000000000: IA32_MTRR_FIX4K_E8000 0x000e8000 - 0x000effff: UC 0x0000000000000000: IA32_MTRR_FIX4K_F0000 0x000f0000 - 0x000f7fff: UC 0x0000000000000000: IA32_MTRR_FIX4K_F8000 0x000f8000 - 0x000fffff: UC 0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB 0x0000007ffff00800: PHYMASK0: Length = 0x0000000000100000, Valid 0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP 0x0000007fff000800: PHYMASK1: Length = 0x0000000001000000, Valid 0x0000000000000000: PHYBASE2 0x0000000000000000: PHYMASK2: Disabled 0x0000000000000000: PHYBASE3 0x0000000000000000: PHYMASK3: Disabled 0x0000000000000000: PHYBASE4 0x0000000000000000: PHYMASK4: Disabled 0x0000000000000000: PHYBASE5 0x0000000000000000: PHYMASK5: Disabled 0x0000000000000000: PHYBASE6 0x0000000000000000: PHYMASK6: Disabled 0x0000000000000000: PHYBASE7 0x0000000000000000: PHYMASK7: Disabled 0x0000000000000000: PHYBASE8 0x0000000000000000: PHYMASK8: Disabled 0x0000000000000000: PHYBASE9 0x0000000000000000: PHYMASK9: Disabled Architectural UPD values for MemoryInit at: 0xfef0fce0 0x01: Revision 0x00000000: NvsBufferPtr 0xfefb0000 --> 0xfef60100: StackBase 0x0004ff00: StackSize 0x00000000 --> 0x00002000: BootLoaderTolumSize 0x00000000: BootMode UPD values for MemoryInit: 0x02: PcdSmmTsegSize 0x00: PcdFspDebugPrintErrorLevel 0xa0: PcdSpdSmbusAddress_0_0 0xa2: PcdSpdSmbusAddress_0_1 0xa4: PcdSpdSmbusAddress_1_0 0xa6: PcdSpdSmbusAddress_1_1 0x00: PcdMrcRmtSupport 0x0c: PcdMrcRmtCpgcExpLoopCntValue 0x06: PcdMrcRmtCpgcNumBursts 0x00: PcdMemoryPreservation 0x01: PcdFastBoot 0x01: PcdEccSupport 0x00: PcdHsuartDevice 0x00 --> 0x01: PcdMemoryDown 0x01: PcdEnableSATA0 0x01: PcdEnableSATA1 0x01: PcdEnableIQAT 0x00: PcdSmbusSpdWriteDisable 0x00: PcdEnableMeShutdown 0x01: PcdEnableXhci 0x06: PcdDdrFreq 0x00: PcdMmioSize 0x01: PcdMeHeciCommunication 0x14: PcdHsioLanesNumber 0x00000000: PcdFiaMuxConfigPtr 0x00: PcdHalfWidthEnable 0x01: PcdTclIdle 0x03: PcdInterleaveMode 0x00: PcdMemoryThermalThrottling 0x00: PcdSkipMemoryTest 0x08: PcdUsb2Port1Pin 0x08: PcdUsb2Port2Pin 0x08: PcdUsb2Port3Pin 0x08: PcdUsb2Port4Pin 0x08: PcdUsb3Port1Pin 0x08: PcdUsb3Port2Pin 0x08: PcdUsb3Port3Pin 0x08: PcdUsb3Port4Pin 0x00: PcdIOxAPIC0_199 0x00: PcdDmapX16 0xfef0fcc0: 44 4e 56 55 50 44 5f 4d 01 00 00 00 00 00 00 00 DNVUPD_M........ 0xfef0fcd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0xfef0fce0: 01 00 00 00 00 00 00 00 00 01 f6 fe 00 ff 04 00 ................ 0xfef0fcf0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 . .............. 0xfef0fd00: 02 00 a0 a2 a4 a6 00 0c 06 00 01 01 00 01 00 10 ................ 0xfef0fd10: f1 fe 01 01 01 00 00 01 06 00 01 14 00 00 00 00 ................ 0xfef0fd20: 76 65 72 73 69 6f 6e 20 78 78 78 00 00 00 00 00 version xxx..... 0xfef0fd30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0xfef0fd40: 00 01 03 00 00 00 00 00 00 08 08 08 08 08 08 08 ................ 0xfef0fd50: 08 00 00 01 01 00 00 00 00 00 00 00 00 00 00 00 ................ 0xfef0fd60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... 0xfef0feb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 aa 55 ...............U Calling FspMemoryInit: 0xfff32450 0xfef0fcc0: raminit_upd 0xfef10f6c: &hob_list_ptr Timestamp - calling FspMemoryInit: 4524096604 Any help on this is highly appreciated . Thanks Somanna Ankaiah

2 3

RFC: Deprecating VBOOT_VBNV_CMOS
by Yu-Ping Wu 15 Aug '22

15 Aug '22

Hi, There's an ongoing effort to expand vboot nvdata (nvstorage) from 16 to 64 bytes [issue <https://issuetracker.google.com/issues/172342278>]. To reduce unnecessary complexity of our firmware code accessing nvdata, we'd like to drop 16-byte nvdata support from the firmware codebase (crossystem still needs to support both though). One obstacle is the CMOS nvdata backend (VBOOT_VBNV_CMOS). We're not sure if there would be enough CMOS space for all boards using that. In addition, because CMOS loses state when the battery is removed, newer boards usually select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH to backup nvdata to flash. Considering that, this seems like a good opportunity to migrate CMOS to flash nvdata [issue <https://issuetracker.google.com/issues/235293589>]. One problem we faced is that many old platforms such as broadwell don't support writing to the flash in early stages (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES). Therefore it looks like we'd need to drop vboot support on them (for example CB:65782 <https://review.coreboot.org/c/coreboot/+/65782>). An alternative would be to keep the CMOS backend around as "deprecated" and not allow 64-byte nvdata for it, but that would at best be a transitory solution for a couple of years, not forever. If there's any concern, please let me know. We have firmware branches for ChromeOS devices, so modifying ToT code wouldn't affect old devices in any way. However, I'm not sure how non-ChromeOS boards (such as mainboard/lenovo/haswell) would be affected by this. Please cc more people if needed. -- Yu-Ping Wu | Software Engineer | yupingso(a)google.com | +886 937 057 080

2 4

Compatibility with legacy boards
by Benoît Dufour 13 Aug '22

13 Aug '22

Hello, I saw one of my old board is listed compatible on the CoreBoot wiki : https://www.coreboot.org/Board:asus/p5gc-mx but knowing the wiki is "being retired". I don't know if it is still supported by the latest version of CoreBoot. Then the Status (as of commit 5bb27b7815) chart has broken colors. So it is hard to me to tell if everything is working fine or not. Then my board is the P5GC-MX/1333 and not the P5GC-MX. I could attempt to flash the Coreboot BIOS to it, but I would want to know if it could bring me some advantages other than "it is free software". For example, the original manufacturer BIOS doesn't supports booting from USB, does CoreBoot supports it?

3 2

Heads up: Allocator changes
by Nico Huber 10 Aug '22

10 Aug '22

Hi coreboot fellows, after two years with the new resource allocator it's time again for some changes[1]. Much less invasive than last time, but again there will be changes in the pattern where resources are placed. So once more this may uncover bugs in case fixed resources are not reserved properly. Reasons for the changes are somewhat the same as always: we haven't finished the support for 64-bit resources. Currently one has to opt in for a placement above 4G with a resource flag, and even this has its limitations. For instance, reserved space for hot-pluggable de- vices can be placed above 4G with a Kconfig setting, but there's no rule what should happen with the resources of cold-plugged devices. In the worst case, allocation for those can fail. Another reason are approaching changes to support multiple PCI host bridges and multiple resource windows per domain. I digress... So everybody is invited to test the patch train. There is a new Kconfig option RESOURCE_ALLOCATION_TOP_DOWN. The default y should work fine, though in case of regressions it would be nice to have it tested with both settings. Cheers, Nico [1] https://review.coreboot.org/q/topic:allocator+status:open

1 1

APOLLOLAKE FSP can find FIT signature
by roman perepelitsin 10 Aug '22

10 Aug '22

Trying to run coreboot on apollo lake atom CPU. I'm stopped at romstage - on call FspMemoryInit I get this message (from debug FSP): FitHeader signature was invalid. As I understood - this mean that FSP can't validate FIT header in memory: "_FIT_ ". I have no ideas what going wrong. I'm doing all by guidlines and recomendations - but have this problem. Also, what mean this coreboot out: CBFS: Unmatched 'filename' at 'offset' ? Thanks! -- regards, Perepelitsin Roman

1 0

ASUS P8ZZ7-V i7-3770 >16GB RAM: SPD CRC failed
by Nico Rikken 09 Aug '22

09 Aug '22

I'm in the process of building a new computer based on the P8ZZ7-V board with a i7-3770 CPU. I am running into a odd behavior the CPU_LED is blinking when using more than 2 8GB RAM modules. This occurs with both the vendor BIOS and the Coreboot build. A friend has the same configuration (mainboard, cpu, 4x8GB memory) which is working just fine. Which make me wonder why my setup is failing. We have gathered serial output (below) to diagnose the issue. Most notable is that for the failing memory configurations the '[DEBUG] Stored timings CRC16 mismatch.' message is returned, after which `[DEBUG] SPD probe channel0, slot1` is triggered, which seems to fail: `ERROR: SPD CRC failed!!!` The resulting looping sequence in the logs: <start of loop> [NOTE ] coreboot-4.17 Fri Jun 3 03:10:05 UTC 2022 bootblock starting (log level: 7)... [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000. [DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4 [DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes) [INFO ] CBFS: mcache @0xfeff0e00 built for 13 files, used 0x2dc of 0x4000 bytes [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14c38 in mcache @0xfeff0e2c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 43 ms [NOTE ] coreboot-4.17 Fri Jun 3 03:10:05 UTC 2022 romstage starting (log level: 7)... [DEBUG] SMBus controller enabled [DEBUG] Setting up static northbridge registers... done [DEBUG] Initializing Graphics... [DEBUG] Back from systemagent_early_init() [INFO ] Intel ME early init [INFO ] Intel ME firmware is ready [DEBUG] ME: Requested 0MB UMA [DEBUG] Starting native Platform init [DEBUG] DMI: Running at X4 @ 5000MT/s [DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) [DEBUG] Stored timings CRC16 mismatch. [DEBUG] ECC supported: no ECC forced: no [INFO ] ECC RAM unsupported. [DEBUG] SPD probe channel0, slot0 [DEBUG] Revision : 11 [DEBUG] Type : b [DEBUG] Key : 2 [DEBUG] Banks : 8 [DEBUG] Capacity : 4 Gb [DEBUG] Supported voltages : 1.5V [DEBUG] SDRAM width : 8 [DEBUG] Bus extension : 0 bits [DEBUG] Bus width : 64 [DEBUG] FTB timings : yes [DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6 [DEBUG] Thermal features : PASR ext_temp_range [DEBUG] Thermal sensor : no [DEBUG] Standard SDRAM : yes [DEBUG] Rank1 Address bits : mirrored [DEBUG] DIMM Reference card: B [DEBUG] Manufacturer ID : 9e02 [DEBUG] Part number : CML16GX3M2A1600C [DEBUG] XMP Profile : 1 [DEBUG] Max DIMMs/channel : 1 [DEBUG] XMP Revision : 1.3 [DEBUG] Requested voltage : 1500 mV [DEBUG] XMP profile supports 1 DIMMs, but 2 DIMMs are installed. [WARN ] XMP maximum DIMMs will be ignored. [INFO ] Row addr bits : 16 [INFO ] Column addr bits : 10 [INFO ] Number of ranks : 2 [INFO ] DIMM Capacity : 8192 MB [INFO ] CAS latencies : 6 9 [INFO ] tCKmin : 1.250 ns [INFO ] tAAmin : 11.250 ns [INFO ] tWRmin : 15.000 ns [INFO ] tRCDmin : 11.250 ns [INFO ] tRRDmin : 7.500 ns [INFO ] tRPmin : 11.250 ns [INFO ] tRASmin : 30.000 ns [INFO ] tRCmin : 50.625 ns [INFO ] tRFCmin : 260.000 ns [INFO ] tWTRmin : 7.500 ns [INFO ] tRTPmin : 7.500 ns [INFO ] tFAWmin : 37.500 ns [INFO ] tCWLmin : 10.000 ns [INFO ] tCMDmin : 2 [DEBUG] channel[0] rankmap = 0x3 [DEBUG] SPD probe channel0, slot1 [DEBUG] ERROR: SPD CRC failed!!! [DEBUG] Revision : 11 [DEBUG] Type : b [DEBUG] Key : 2 [DEBUG] Banks : 8 [DEBUG] Capacity : 4 Gb [DEBUG] Supported voltages : 1.5V [DEBUG] SDRAM width : 8 [DEBUG] Bus extension : 0 bits [DEBUG] Bus width : 64 <end of loop, restarting Coreboot> Mainboard: ASUS P8ZZ7-V CPU: i7-3770 RAM 4x8GB DDR3 Corsair CML16GX3M2A1600C9 Does anybody have advise what could be causing the `SPD CRC failed!!!` error? The next idea is to replace the CPU as the memory seems fine to swap around in most configurations. Other ideas are the motherboard, or something interfering with the readout. Is there an easy way to perhaps hardcode my way out of it for now, knowing the RAM will remain there once configured so I could even doe a custom Coreboot build? Best, Nico

4 7

Reconsidering the Gerrit submission strategy
by Patrick Georgi 08 Aug '22

08 Aug '22

Hi everybody, I was recently made aware that Gerrit now supports adding metadata to commit messages in the "rebase" strategy. The "cherry-pick" strategy that we're using has been chosen over everything else primarily due to this capability. Some details: Gerrit supports different ways of committing changes into branches when developers submit them, with different effects on which changes are considered ready and how they show up in the commit history. The two main contenders are "cherry-pick" and "rebase always". Both create a linear history (unlike some "merge" strategies that can create merge commits. Both add metadata to the commits, all that "Reviewed-on", "Reviewed-by" etc in the commit message. Cherry-pick considers every change on Gerrit on its own. Even if you push a patch train of 50 commits, it allows submitting commit #49 individually. That gives some flexibility (if these commits are truly independent) but also creates risk: if changes are merged out of order, we might break the tree with otherwise perfectly good commits, for example when a new API is used that is only added by a previous commit. Rebase always considers patch trains: To submit commit #49, the commit itself and all its 48 ancestors need to be ready for submission. It becomes a one-click operation in the UI and ordering is honored. On the other hand, picking an individual commit is a manual operation now (cherry-pick to become its own patch train, push, re-review). Speaking of UI, depending on the strategy the "readiness" marker in the UI changes behavior, too: With "cherry-pick", each commit is compared against the branch individually, with a "merge conflict" notification if the commit on its own would fail to merge. With "rebase always" the entire patch train up to that point is considered. It's a matter of trade-offs, but given that "rebase always" can now add the metadata that was the deal breaker for anything but cherry-pick back in the day, I wanted to know how y'all feel about changing or keeping the submission strategy. David proposed that we could try out "rebase always" for a while (maybe a month) to see how it feels. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Liana Sebastian

6 19

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