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RE: [COMMIT] epia-m support
by hcyun＠etri.re.kr 27 Apr '03

27 Apr '03

Well, I also made a linuxbios port for epia-m and ADLO and bochs bios patch which can run original vgabios of epia-m (Adam helped me a lot). So I can see vga text console and also I can run XFree86 or what so ever. And also my collegue made a framebuffer driver. However, because of NDA, I'm afraid I can't share it with you for now. (I don't know anything about specific details of NDA, but my boss told me to do so until our project is done). However, as for ADLO, I think If you have the CLE266 programming guide, you can do it by implementing bios APIs of chapter 7 onto bochs bios code and slight modification of loader.s of ADLO. BTW, Andrew I have a question to you how you can release code. You may need via documents which require NDA. Is VIA approved or sponsoring you? Regard, Heechul > -----Original Message----- > From: Andrew Ip [mailto:aip@cwlinux.com] > Sent: Sunday, April 27, 2003 5:24 PM > To: Adam Sulmicki > Cc: linuxbios(a)clustermatic.org > Subject: Re: [COMMIT] epia-m support > > > Adam, > > > Sounds like great news. Now if I only had an EPIA-M board :-P > > FYI: people have gotten VGA and ADLO (fully working; with > VGA!) to work > > successfully under EPIA-M. It seems there may be some NDA's > issues to it > > may be few months before they can contribute back. > Is it? I would like to try it first. > > -Andrew > > -- > Andrew Ip > Email: aip(a)cwlinux.com > Tel: (852) 2542 2046 > Fax: (852) 2542 2036 > Mobile: (852) 9201 9866 > > Cwlinux Limited > Unit 202B 2/F Lai Cheong Factory Building, > 479-479A Castle Peak Road, > Lai Chi Kok, Kowloon, > Hong Kong. > > Tel: (852)2542 2046 > Fax: (852)2542 2036 > > For public pgp key, please obtain it from http://www.keyserver.net/en. > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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[COMMIT] epia-m support
by Andrew Ip 27 Apr '03

27 Apr '03

I'm pleased to announce EPIA-M is now supported. I would like to thank Nougen for sponsoring this. At this moment, the checkin supports ddr ram init, etherboot, linux and proper irq routing. However, VGA is not done. There is bug where serial baudrate always start in 57600 from cold boot even 115200 is set, but reset from award bios works fine. -Andrew -- Andrew Ip Email: aip(a)cwlinux.com Tel: (852) 2542 2046 Fax: (852) 2542 2036 Mobile: (852) 9201 9866 Cwlinux Limited Unit 202B 2/F Lai Cheong Factory Building, 479-479A Castle Peak Road, Lai Chi Kok, Kowloon, Hong Kong. Tel: (852)2542 2046 Fax: (852)2542 2036 For public pgp key, please obtain it from http://www.keyserver.net/en.

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post data on sis950 lpt
by Felix Kloeckner 27 Apr '03

27 Apr '03

hi, some time ago i made linuxbios successfully running on the elitegroup p6stp-fl. because i am using the onboard parallel port (sis950) i found that the port will be correctly switched on, but it's left in "post data port" mode. i modified "src/superio/sis/950/superio.c" so post data port mode will be switched off. may someone patch that file or does anybody need the parallel port in that mode? (patch is attached) felix

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setting USE_ELF_BOOT
by Shubhangi Jadhav 26 Apr '03

26 Apr '03

Hi, When do we need to set USE_ELF_BOOT option ? Is elfboot loader required to load ADLO ? or is it required only in case of etherboot? Regards, Shubhangi

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Re: Polling IDE and CF issue.
by ebiederman＠lnxi.com 25 Apr '03

25 Apr '03

Richard Smith <rsmith(a)bitworks.com> writes: > Eric W. Biederman wrote: > > > Adam Agnew <agnew(a)cs.umd.edu> writes: > > >>Sorry I have to ask, but.. which polled ide code are you talking about? > >>LinuxBIOS native, Etherboot 5.0.6 or Etherboot 5.1.7? > > Given that the mentioned command does not occur in etherboot > > 5.1.7 it sounds like the builtin IDE driver. Richard please > > try the etherboot one. Ron was looking at backporting it. > > > Correct. its the LinuxBIOS native one. > > > There are no magic delay funnies and the code has been tested > > with quite a few drives. > > Ok so that would be go get Etherboot 5.1.7 compile it so it includes IDE right? > Does the make file create an Elf image or do I have to use mkelfimage? mkelfImage is not required. make ide_disk.zelf or make nic1--nic2--nic3--ide_disk.zelf. It's weird but it allows etherboot to build multiple drivers. 5.1.8 now that it is released is probably better. I need to see how well make etherboot.zelf and make etherboot-pci.zelf work. The first one includes all of the drivers and the second one includes all of the pci drivers (which should include ide_disk). > Which mainbord has a good config file example for this? Basically you just need to use the ELF bootloader. Eric

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linuxbios problem
by Shubhangi Jadhav 25 Apr '03

25 Apr '03

Hi, I'm trying to get my motherboard working with Linuxbios. I'm using ADLO with Linuxbios. The debug messages are as below. The problem is after jumping to linuxbiosmain (it prints "Welcome to start32......") it loops back , restarting the boot process all over again. what's wrong ? why does it go in a loop? ***************log********************************* LinuxBIOS-1.0.0 Thu Apr 24 06:42:06 IST 2003 starting... Ram1 Ram2 Ram3 Ram Enable 1 Ram Enable 2 Ram Enable 3 Ram Enable 4 Ram Enable 5 Ram4 Ram5 Ram6 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.0.0 Thu Apr 24 06:42:06 IST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 handle_superio start, nsuperio 1 handle_superio Pass 0, check #0, s 0000cde0 s->super 0000e138 handle_superio: Pass 0, Superio w83627hf handle_superio port 0x0, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 0, done #0 handle_superio done Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [8086/7124] PCI: 00:1e.0 [8086/2418] PCI: 00:1f.0 [8086/2410] PCI: 00:1f.1 [8086/2411] PCI: 00:1f.2 [8086/2412] PCI: 00:1f.3 [8086/2413] PCI: 00:1f.5 [8086/2415] PCI: 00:1f.6 [8086/2416] PCI: pci_scan_bus for bus 1 PCI: 01:04.0 [10ec/8139] PCI: 01:05.0 [10ec/8139] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done Allocating PCI resources... ASSIGN RESOURCES, bus 0 PCI: 00:1e.0 1c <- [0x00001000 - 0x00001fff] bus 1 io PCI: 00:1e.0 24 <- [0xfec00000 - 0xfebfffff] bus 1 prefmem PCI: 00:1e.0 20 <- [0xfeb00000 - 0xfebfffff] bus 1 mem ASSIGN RESOURCES, bus 1 PCI: 01:04.0 10 <- [0x00001000 - 0x000010ff] io PCI: 01:04.0 14 <- [0xfeb00000 - 0xfeb000ff] mem PCI: 01:05.0 10 <- [0x00001400 - 0x000014ff] io PCI: 01:05.0 14 <- [0xfeb01000 - 0xfeb010ff] mem ASSIGNED RESOURCES, bus 1 PCI: 00:1f.1 20 <- [0x000028e0 - 0x000028ef] io PCI: 00:1f.2 20 <- [0x000028c0 - 0x000028df] io PCI: 00:1f.3 20 <- [0x000028f0 - 0x000028ff] io PCI: 00:1f.5 10 <- [0x00002000 - 0x000020ff] io PCI: 00:1f.5 14 <- [0x00002880 - 0x000028bf] io PCI: 00:1f.6 10 <- [0x00002400 - 0x000024ff] io PCI: 00:1f.6 14 <- [0x00002800 - 0x0000287f] io ASSIGNED RESOURCES, bus 0 done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:1e.0 cmd <- 07 PCI: 00:1f.0 cmd <- 0f PCI: 00:1f.1 cmd <- 01 PCI: 00:1f.2 cmd <- 01 PCI: 00:1f.3 cmd <- 01 PCI: 00:1f.5 cmd <- 01 PCI: 00:1f.6 cmd <- 01 PCI: 01:04.0 cmd <- 03 PCI: 01:05.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized DRP0 = 0x9 DIMM0 - size = 64M DIMM1 - size = 0M DRP1 = 0x0 DIMM2 - size = 0M totalram: 64M Initializing CPU #0 Updating microcode microcode_info: sig = 0x00000678 pf=0x00000001 rev = 0x00000000 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 64MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : CentaurHauls Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x07 Processor Mask : 0x00 Processor Stepping : 0x08 Feature flags : 0x00803035 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Configuring L2 cache...Not 'GenuineIntel' Processor Enable Cache done. Disabling local apic...done. CPU #0 Initialized ioapic southbridge enabled 180 RTC Init Invalid CMOS LB checksum set power on after power fail Please turn on nvram handle_superio start, nsuperio 1 handle_superio Pass 1, check #0, s 0000cde0 s->super 0000e138 handle_superio: Pass 1, Superio w83627hf handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Call init Enabling com device: 03 iobase = 0x02f8 irq=3 handle_superio Pass 1, done #0 handle_superio done handle_superio start, nsuperio 1 handle_superio Pass 2, check #0, s 0000cde0 s->super 0000e138 handle_superio: Pass 2, Superio w83627hf handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 2, done #0 handle_superio done Wrote linuxbios table at: 00000500 - 00000664 checksum 7535 Jumping to linuxbiosmain()... Welcome to start32, the open sourced starter. This space will eventually hold more diagnostic information. January 2000, James Hendricks, Dale Webster, and Ron Minnich. Version 0.1 LinuxBIOS-1.0.0 Thu Apr 24 06:42:06 IST 2003 starting... Ram1 Ram2 Ram3 Ram Enable 1 Ram Enable 2 Ram Enable 3 Ram Enable 4 Ram Enable 5 Ram4 Ram5 Ram6 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. ***************log********************************* Regards, Shubhangi

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help: flash an epia
by Philippe CABANNES 25 Apr '03

25 Apr '03

I'm sorry but i still have problems. the setpci command looks ok. thanks ;-) When i execute the makefile i don't have error anymore but i can't run flash_rom. I've read this : >Basically you need flash_rom to flash romimage. It can be built from >cvs >tree(freebios/util/flash_and_burn). Here is the step to flash, >1. enable flash writable >$ setpci -s 0:11.0 40.b=3D54 >2. flash romimage >$ flash_rom romimage but when i execute "flash_rom romimage" it says me "command not found" -------------------------------------------------- Oreka ! Nous sommes l'internet moins cher ! Surfez 25% moins cher avec http://www.oreka.com

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help : flash an epia
by Philippe CABANNES 25 Apr '03

25 Apr '03

I want to load linuxbios on an epia board. When i try to execute the flash_rom utility it compile the different file and give me this mistake: flash_rom.c:35: pci/pci.h: No such file or directory make: *** [all] Error 1 I´ve put rhe romimage into the directory /util/flash_and_burn and executed the makefile I also tried the command "setpci -s 0:11.0 40.b=3D54" but it gives an error of syntax... So how should i do? Thanks im advance. -------------------------------------------------- Oreka ! Nous sommes l'internet moins cher ! Surfez 25% moins cher avec http://www.oreka.com

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[ANNOUNCE] mkelfImage-2.5
by ebiederman＠lnxi.com 25 Apr '03

25 Apr '03

At: ftp://ftp.lnxi.com/pub/src/mkelfImage/mkelfImage-2.5.tar.gz * 2.5 24 April 2003 - Fix the checksum code so that it checksums the bss sections as well. How I missed the checksum code was broken in 2.4 I don't know. Eric

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Debugging the linuxBIOS code
by dkotian3＠vsnl.net 24 Apr '03

24 Apr '03

Hi, Is there a recommended way of debugging LinuxBIOS code. I burnt my FLASHROM with LinuxBIOS, nothing came up at all. Not a single message came at the serial Output. I knew that my North bridge code has issues, but still something should have come. I guess.. I had connected the serial out of my PC to another PC and I am using an Windows HyperTerminal to view the messages. Should it not show something at all even if north bridge code is broken. Could anyone give their views on this one.. Regards Deepak

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