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39782 discussions

PC2700 and funny effects.
by Stefan Reinauer 19 Nov '03

19 Nov '03

When using PC2700 ECC memory in a Solo machine, it seems to clear only the first 31 bytes(?) and then repeat jumping to it's rammed copy endlessly SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 disabling dimm01 disabling dimm01 166Mhz disabling dimm01 RAM: 0x00080000 KB Ram3 ECC enabled Initializing memory: done Clearing memory: addr 00000000-0000001f --------done Copying LinuxBIOS to ram. Jumping to LinuxBIOS. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. [ad nauseum] Stefan -- Stefan Reinauer, SUSE LINUX AG Teamleader Architecture Development

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Re: Off by eight.
by Jordan Archer 19 Nov '03

19 Nov '03

How does the fallback version get executed? Stepping through the reset sequence it looks from my image that that's the default. Jordan At 02:52 PM 11/18/2003, ron minnich wrote: >On Tue, 18 Nov 2003, Jordan Archer wrote: > > > I'm pretty sure that it's not 32 bit reset code. The problem appears if I > > try to build an image without a fallback. > >oh. When I try to build an image without a fallback (this part is >counterintuitive) I always just build a fallback. Possibly that's the >wrong thing to do :0) > >ron

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Address mapping?
by Devi Priya 19 Nov '03

19 Nov '03

I am using sc1200. To which physical address does the flash memory and sdram mapped in linuxbios? _________________________________________________________________ Enjoy shopping online? Get this e credit card. http://server1.msn.co.in/features/amex/ It cuts cost & adds value!

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Porting
by Joshua Wise 18 Nov '03

18 Nov '03

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi all, I've got a ABIT KG7-RAID board here that I'd like to port LinuxBIOS to (and a school vacation coming up that I was planning to be bored over.) There used to be a page that had info on that, but my bookmark seems to be broken. Can someone tell me what data I will need to gather to determine how much work I'll need to do, and what tools I'll need? I read that you guys use DoCs and BIOS saviors - do the DoCs work through the BIOS saviors? or will I have to hot-swap flash chips? Thanks, joshua - -- Joshua Wise | www.joshuawise.com GPG Key | 0xEA80E0B3 Quote | <lilo> I akilled *@* by mistake -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.2 (GNU/Linux) iD8DBQE/urRAPn9tWOqA4LMRAoNAAJ9vCO9NyX1mO8ZoQWoSDp9kXVM0xwCeKHtb emKr1TaOdJ1nYZFQSQ+gFIk= =Vd/d -----END PGP SIGNATURE-----

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Etherboot fail to initialize RTL8139 on linuxbios
by riskin＠esinosoft.com 18 Nov '03

18 Nov '03

Hello all, My etherboot(5.0.9) payload on linuxbios failed to initialize RTL8139 successfully,but the payload inculded RTL8139 codes. But LinuxBIOS has already initialized the RTL8139 ,because when the system was booted from IDE,RTL8139 can work well. Could somebody help me?Thanks! riskin Boot Messages: LinuxBIOS-1.0.0 Tue Nov 18 13:48:39 CST 2003 starting... Enabled first bank of RAM: 0x04000000 bytes Copying LinuxBIOS to ram. Jumping to LinuxBIOS. POST: 0x39 LinuxBIOS-1.0.0 Tue Nov 18 13:48:39 CST 2003 booting... POST: 0x40 Finding PCI configuration type. PCI: Using configuration type 1 POST: 0x5f Scanning PCI bus...PCI: pci_scan_bus for bus 0 POST: 0x24 PCI: 00:00.0 [1106/0601] PCI: 00:01.0 [1106/8601] PCI: 00:07.0 [1106/0686] PCI: 00:07.2 [1106/3038] PCI: 00:07.3 [1106/3038] PCI: 00:07.4 [1106/3057] PCI: 00:07.5 [1106/3058] PCI: 00:07.6 [1106/3068] PCI: 00:0e.0 [10ec/8139] POST: 0x25 PCI: pci_scan_bus for bus 1 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=01 POST: 0x55 PCI: pci_scan_bus returning with max=01 POST: 0x55 done POST: 0x66 Allocating PCI resources... PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it ASSIGN RESOURCES, bus 0 PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io PCI: 00:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 1 prefmem PCI: 00:01.0 20 <- [0xfeb00000 - 0xfeafffff] bus 1 mem PCI: 00:07.2 20 <- [0x00001c00 - 0x00001c1f] io PCI: 00:07.3 20 <- [0x00001c20 - 0x00001c3f] io PCI: 00:07.5 10 <- [0x00001000 - 0x000010ff] io PCI: 00:07.5 14 <- [0x00001c40 - 0x00001c43] io PCI: 00:07.5 18 <- [0x00001c50 - 0x00001c53] io PCI: 00:07.6 10 <- [0x00001400 - 0x000014ff] io PCI: 00:0e.0 10 <- [0x00001800 - 0x000018ff] io PCI: 00:0e.0 14 <- [0xfeb00000 - 0xfeb000ff] mem ASSIGNED RESOURCES, bus 0 done. POST: 0x88 Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 cmd <- 07 PCI: 00:07.0 cmd <- 87 PCI: 00:07.2 cmd <- 01 PCI: 00:07.3 cmd <- 01 PCI: 00:07.4 cmd <- 00 PCI: 00:07.5 cmd <- 01 PCI: 00:07.6 cmd <- 01 PCI: 00:0e.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized POST: 0x89 Disable Cache Bank4 64MB (MA type 0x8) Enable Cache Total 64MB + frame buffer 0MB Enabling shadow DRAM at 0xC0000-0xFFFFF: done POST: 0x70 totalram: 64M Initializing CPU #0 POST: 0x60 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB Setting fixed MTRRs(24-88) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 64MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs POST: 0x6a done. Max cpuid index : 1 Vendor ID : CentaurHauls Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x07 Processor Mask : 0x00 Processor Stepping : 0x03 Feature flags : 0x00803035 POST: 0x92 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Disabling local apic...done. POST: 0x9b CPU #0 Initialized Mainboard fixup IDE enable in reg. 48 is 0x3 set IDE reg. 48 to 0x1 IRQs in reg. 4a are 0x4 setting reg. 4a to 0xc4 enables in reg 0x42 0xc9 enables in reg 0x42 read back as 0x9 IDE enable in reg.1-40 is 0x8 set IDE reg.1-40 to 0xb IDE enable in reg.1-40 read back is 0xb enables in reg 0x9 0x8f enables in reg 0x9 read back as 0x8a command in reg 0x4 0x80 command in reg 0x4 reads back as 0x7 pci_routing_fixup: dev is 000125e4 setting southbridge Assigning IRQ 11 to 0:7.2 Readback = 11 Assigning IRQ 11 to 0:7.3 Readback = 11 Assigning IRQ 12 to 0:7.5 Readback = 12 setting ethernet Assigning IRQ 11 to 0:e.0 Readback = 11 setting pci slot pci_routing_fixup: DONE POST: 0x75 POST: 0x77 POST: 0x91 POST: 0x92 POST: 0x95 Final mainboard fixup Southbridge fixup IDE enable in reg. 48 is 0x1 set IDE reg. 48 to 0x1 IRQs in reg. 4a are 0x4 setting reg. 4a to 0xc4 enables in reg 0x42 0x9 enables in reg 0x42 read back as 0x9 IDE enable in reg.1-40 is 0xb set IDE reg.1-40 to 0xb IDE enable in reg.1-40 read back is 0xb enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x7 command in reg 0x4 reads back as 0x7 pci_routing_fixup: dev is 000125e4 setting southbridge Assigning IRQ 11 to 0:7.2 Readback = 11 Assigning IRQ 11 to 0:7.3 Readback = 11 Assigning IRQ 12 to 0:7.5 Readback = 12 setting ethernet Assigning IRQ 11 to 0:e.0 Readback = 11 setting pci slot pci_routing_fixup: DONE POST: 0xec POST: 0x9a Checking IRQ routing tables... /home/chenyq/linuxbios/filo+bios8601/bios8601/src/arch/i386/lib/pirq_routing.c: 30:check_pirq_routing_table() - irq_routing_table located at: 0x00009ac0 done. Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...succeed POST: 0x96 Wrote linuxbios table at: 00000500 - 0000068c checksum 98 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 POST: 0xf8 37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 New segment addr 0x94000 size 0x7c68 offset 0x80 filesize 0x3474 (cleaned up) New segment addr 0x94000 size 0x7c68 offset 0x80 filesize 0x3474 Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007c68 filesz: 0x0000000000003474 Clearing Segment: addr: 0x0000000000097474 memsz: 0x00000000000047f4 Jumping to boot code at 0x94000 POST: 0xfe ROM segment 0x7191 length 0xbffe reloc 0x9400 Etherboot 5.0.9 (GPL) ELF for [RTL8139] routerd etherboot version 1.0.0 Probing...[RTL8139]Found Realtek 8139 ROM address 0x0000 - to enable rtl8139 rtl8139 old command 263 rtl8139 new command 263 ioaddr 0X1800, addr 00:0D:87:36:2B:ED 10Mbps half-duplex Cable not connected or other link failure No adapter found <sleep> 0 LinuxBIOS-1.0.0 Tue Nov 18 13:48:39 CST 2003 starting... Enabled first bank of RAM: 0x04000000 bytes Copying LinuxBIOS to ram. Jumping to LinuxBIOS. POST: 0x39 LinuxBIOS-1.0.0 Tue Nov 18 13:48:39 C ...

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re: About Hardreset on Opteron MB
by YhLu 18 Nov '03

18 Nov '03

noisy smbus? -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2003年11月18日 15:17 收件人: Stefan Reinauer 抄送: YhLu; 'linuxbios(a)clustermatic.org' 主题: Re: About Hardreset on Opteron MB Stefan Reinauer <stepan(a)suse.de> writes: > * YhLu <YhLu(a)tyan.com> [031118 22:50]: > > I have checked the latest code again for Opteron MB. The MB still needs to > > reset three times to get it done. > > > Can we only reset the MB only time to make the HT work at the need > > speed/width? > > It should be enough to set a global variable "reset_needed" (maybe even > in CMOS) and check this, probably after all device drivers have been > executed and thus had the chance to set that flag. > > > I mean only enable the reset in > > PCI: 00:19.3 init > > NB: Function 3 Misc Control.. resetting cpu > > When changing the parameters on Solo I always got it to one of the > reboots - My best result was to get it to the Misc Control reset before > it would hang hard. Reducing the number of reboots definitely needs to happen. I only coded the way it is currently because that generates obviously correct code. Right now I am looking at how to reduce problems when a board has a noisy smbus. So far I have not seen a single board without one. In the noisy smbus the more traffic you have the more chances there are you will have problems because of it. So it might make sense to set everything up in a very early pass before memory reset. Reset the system, and then let the existing resets will not trigger. Either that or Stefans delayed scheme. At this point I am not certain which will be easier to maintain. If we do implement the delayed reset I want to move the memory clear code up into the generic framework so we don't have to clear memory twice. But if we can get the resets over with before we initialize memory we are in better shape. That plus something like the kernels quirk interface to handle the various know bits of buggy hardware and we should be ok. Eric

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About Hardreset on Opteron MB
by YhLu 18 Nov '03

18 Nov '03

Eric, I have checked the latest code again for Opteron MB. The MB still needs to reset three times to get it done. 1. Hyper transport scan link: 0 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed 2. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. resetting cpu 3. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.3 init NB: Function 3 Misc Control.. resetting cpu Can we only reset the MB only time to make the HT work at the need speed/width? I mean only enable the reset in PCI: 00:19.3 init NB: Function 3 Misc Control.. resetting cpu Regards YH

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Off by eight.
by jarcher＠pobox.com 18 Nov '03

18 Nov '03

I'm generating an new CPU, SB and motherboard. I got the build up and running, but my image is off by eight bytes. The reset code that should be at the top of the ROM (xxxxFFF0) is at xxxxFFF8, so I'm short 8 bytes in the ROM image file. Anyone have a clue as to what I should look at to trace this down? Jordan

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".config" file for epia-m
by Xavier Pegenaute 18 Nov '03

18 Nov '03

Hi, anyone have a .config file for epia-m to put it as payload? at the moment my bzImage.elf is about 319Kb. Is it possible with epia and normal flash rom? Thanks.

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the really good news about i2c (smbus)
by ron minnich 18 Nov '03

18 Nov '03

SMBUS/I2C is a noisy, glitchy, buggy mess that can hang motherboards. And the motherboards, more and more, are depending on it working correctly for all their management functions. The PC world is really amazing sometimes. ron

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