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Filesystem for DOCM?
by Devi Priya 31 Dec '03

31 Dec '03

Hi, Which file system should I use for diskonchip millennium while using with linuxbios? _________________________________________________________________ Free transactions in any ATM across India. http://server1.msn.co.in/msnleads/suvidha/dec03.asp?type=hottag Click here.

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Re: Flash mapped to lower address?
by Bari Ari 26 Dec '03

26 Dec '03

Devi Priya wrote: > I like to use either Flash memory or DOC and not both. I want to know if > I have my Flash memory or DOC mapped to lower address what modification > should I do to the linuxbios coding. like regarding setiing the RAMBASE, > ROMBASE........... > The power-up reset address for the Geode is FFFFFFF0h, you can't change that. Your only strapping options are: (1) Enable either an 8 bit or 16 bit boot ROM access (2) Enable either a LPC or ISA boot ROM access. -Bari > Regards, > Priya. > > >> From: Bari Ari <bari(a)onelabs.com> >> To: Devi Priya <ijpriya(a)hotmail.com> >> CC: linuxbios(a)clustermatic.org >> Subject: Re: Flash mapped to lower address? >> Date: Fri, 26 Dec 2003 20:45:41 -0600 >> >> >> >> Devi Priya wrote: >> >>> If i have my Flash memory mapped to the lower address >>> (0x0000-0x3FFFFF), then what modification should be made to linux bios? >> >> >> Are you using NAND Flash or DOC or both ? Are you trying to boot from >> the DOC? >> >> You may also want to look at the >> >> Geode™ IA on a Chip Devices: Booting from the M-Systems DiskOnChip >> Millennium Application Note >> >> http://www.m-sys.com/files/documentation/doc/App_Note_047_Des_DOC_FD_Boot_R… >> >> >> http://www.m-sys.com/files/documentation/doc/App_Note_031_PC_Rev_2.2.pdf >> >> -Bari >> >> >> >> _______________________________________________ >> Linuxbios mailing list >> Linuxbios(a)clustermatic.org >> http://www.clustermatic.org/mailman/listinfo/linuxbios > > > _________________________________________________________________ > NRI’s, Free Money transfer to India. > http://server1.msn.co.in/msnleads/citibankrca/citibankrca2.asp?type=hottag > Click here. > > >

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Flash mapped to lower address?
by Devi Priya 26 Dec '03

26 Dec '03

If i have my Flash memory mapped to the lower address (0x0000-0x3FFFFF), then what modification should be made to linux bios? _________________________________________________________________ NRIs, Free Money transfer to India. http://server1.msn.co.in/msnleads/citibankrca/citibankrca2.asp?type=hottag Click here.

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Re: Flash mapped to lower address?
by Devi Priya 26 Dec '03

26 Dec '03

Hi, >From the AMD data sheet: The Core Logic module positively decodes memory addresses 000F0000h-000FFFFFh (64 KB) and FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory cycles cause the Core Logic module to claim the cycle, and generate an ISA bus memory cycle with ROMCS# asserted. The Core Logic module can also be configured to respond to memory addresses FF000000h-FFFFFFFFh (16 MB) and 000E0000h-000FFFFFh (128 KB). 8- or 16-bit wide ROM is supported. BOOT16 strap determines the width after reset. MCR[14,3] (Offset 34h) in the General Configuration Block allows program control of the width. Flash ROM is supported in the Core Logic module by enabling the ROMCS# signal on write accesses to the ROM region. Normally only read cycles are passed to the ISA bus, and the ROMCS# signal is suppressed for write cycles. When the ROM Write Enable bit (F0 Index 52h[1]) is set, a write access to the ROM address region causes a write cycle to occur with MEMW#,WR# and ROMCS# asserted. The Boot Flash supported by the SC1200/SC1201 can be up to 16 MB. It is supported with the ROMCS# signal. As the corelogic module positively decodes the memory addresses 000F0000h-000FFFFFh (64 KB) and FFFC0000h-FFFFFFFFh (256 KB) at reset, I can have my Flash memory mapped to the lower address. Is it? >From: ron minnich <rminnich(a)lanl.gov> >To: Devi Priya <ijpriya(a)hotmail.com> >CC: linuxbios(a)clustermatic.org >Subject: Re: Flash mapped to lower address? >Date: Wed, 24 Dec 2003 18:39:20 -0700 (MST) > >On Tue, 23 Dec 2003, Devi Priya wrote: > > > If i have my Flash memory mapped to the lower address (0x0000-0x3FFFFF), > > then what modification should be made to linux bios? > >why on earth would you map flash to this address? it makes no sense to me. > >ron > >_______________________________________________ >Linuxbios mailing list >Linuxbios(a)clustermatic.org >http://www.clustermatic.org/mailman/listinfo/linuxbios _________________________________________________________________ NRIs, Free Money transfer to India. http://server1.msn.co.in/msnleads/citibankrca/citibankrca2.asp?type=hottag Click here.

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EPIA + non-standard flash chip
by Surjan Singh 24 Dec '03

24 Dec '03

Hello, Wondering if anyone can help me with this one: I have a basic EPIA board (http://www.viavpsd.com/product/epia_mini_itx_spec.jsp?motherboardId=21) , the one with the 533MHz CPU. Anyway, I managed to find myself a PLCC Flash chip which seems like it will work (http://www.farnell.com/datasheets/23247.pdf), but when I run the flash program it complains that it does not recognise the chip. So, I added an entry for the chip in "flash.h" hoping I could use the regular routines for the EPIA, but it says it cannot unlock the chip. Can someone help me with this one pls? Could someone supply a diff, using the above datasheet, that would enable me to use the chip? Even some tips on what I'd need to do if I had to write the code would be appreciated. Thanks, Surj

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Re: Success stories
by Hendricks David W. 24 Dec '03

24 Dec '03

Can you be more specific about your mainboard? Chaintech makes dozens of models. Copy / paste your lspci output if possible.

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Success stories
by Kees Meijs 21 Dec '03

21 Dec '03

Hello there, I'd like to flash my ChainTech motherboard with a Linux kernel or just grub. Did anyone did this before? And if so, how did you do it? Cheers, Kees P.S. It's a pity the documentation on the web is very sparse, maybe I can write some?

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Re: EPIA-M serial port 1/2 baud rate insanity
by Dave Ashley 19 Dec '03

19 Dec '03

Andrew Ip wrote: >Have you checked out the clock connected to LPC? On W311, FS2 can be >set to 24 or 48 MHz. It could be the problem, since I have similar problem >with USB on a custom cle266 board. FYI, it can be programmed thru smb. >Here is from we have done to program the USB clock. >... >You may want to put similar code in serial init. Hope this help. I tried this and...it worked! My simple test program is below. Linuxbios puts the smb stuff at 0xf00 and it is already enabled (at least in my patch). So all I had to do was do the outb's to get it to work. Thanks *very* much. Note to Ron: Let me know if you want the epia-m, I'll still send one off if you want it. I've got a spare 10000 (1 gig) that you can have. Note I don't read email sent to the address I'm posting from...best send to dash(a)xdr.com to get to me. #include <stdio.h> #include <string.h> #include <unistd.h> #include <sys/io.h> #include <stdlib.h> #define SMB_STATUS (base + 0) #define SMB_CONTROL (base + 2) #define SMB_COMMAND (base + 3) #define SMB_ADDRESS (base + 4) #define SMB_DATA (base + 5) #define I2C_TRANS_CMD 0x40 #define CLOCK_SLAVE_ADDRESS 0x69 int main(int argc, char **argv) { int res; int base=0xf00; res=iopl(3); if(res) { perror("iopl"); exit(-1); } outb( 0xff, SMB_STATUS ); // USB out 48MHz outb( 0x7f, SMB_DATA ); outb( 0x83, SMB_COMMAND ); outb( (CLOCK_SLAVE_ADDRESS<<1), SMB_ADDRESS ); outb( 0x8|I2C_TRANS_CMD, SMB_CONTROL ); while( inb(SMB_STATUS) & 0x01 ); } -Dave

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Intel 82845G/GL
by Brian Thomason 19 Dec '03

19 Dec '03

I scanned the entire mailing and website for LinuxBIOS and didn't see a single reference to the Intel 82845G/GL. Is this configuration supported? If not, would it be "easy" to add support for it? I'm very new to LinuxBIOS (just discovered the website a month or so ago and still don't fully grok it) but have two machines with this chipset I'd like to get setup as sample boxes to show my boss the increase in boot time. (From what I hear, it speeds up boot time CONSIDERABLY) Thanks in advance for your time, Brian Thomason Lindows.com Developer Relations

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Re: EPIA-M serial port 1/2 baud rate insanity
by Dave Ashley 18 Dec '03

18 Dec '03

Here is what I did to integrate this into linuxbios. I created the following file src/mainboard/via/epia-m/smbusenable.inc /* Useful macros PCIBUS, and SMBUS functions for getting DRAM going. */ /* courtesy Eric Biederman of linuxnetworx.com */ #define CS_WRITE_BYTE(addr, byte) \ movl $addr, %eax ; \ movl $byte, %edx ; \ PCI_WRITE_CONFIG_BYTE #define CS_WRITE_WORD(addr, word) \ movl $addr, %eax ; \ movl $word, %ecx ; \ PCI_WRITE_CONFIG_WORD #define CS_WRITE_LONG(addr, dword) \ movl $addr, %eax ; \ movl $dword, %ecx ; \ PCI_WRITE_CONFIG_DWORD #define DEVFN(device, function) (((device) << 3) + (function)) #ifndef CONFIG_ADDR #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where)) #endif /* generic SMB routines that work for many systems. The only one that might * not work is the enable_smbus. * you have to define PM_FUNCTION for this to work. */#define SMBUS_IO_BASE 0xf00 #define SMBHSTSTAT 0 #define SMBHSTCTL 2 #define SMBHSTCMD 3 #define SMBHSTADD 4 #define SMBHSTDAT0 5 #define SMBHSTDAT1 6 #define SMBBLKDAT 7 /* (DA) Lines added to get this to compile */ #define PM_DEVFN CONFIG_ADDR(0,0x11*8,0) #define DRAM_CONFIG_PORT 0x5a #define SMBUS_MEM_DEVICE_0 0x50 #define LAST_SMBUS_MEM_DEVICE SMBUS_MEM_DEVICE_0 #define REGISTERED_DRAM_REGISTER $0x69 #define REGISTERED_DRAM $0x2d #define NONREGISTERED_DRAM $0 /* put the SMBUS at port 0xf00 + enable*/ CS_WRITE_WORD(PM_DEVFN+ 0xd0, SMBUS_IO_BASE|1) /* iobase addr */ CS_WRITE_BYTE(PM_DEVFN + 0xd2, (0x4 << 1) | 1) /* smbus enable */ CS_WRITE_WORD(PM_DEVFN + 0x4, 1) /* iospace enable */ /* The VT1211 serial port needs 48 mhz clock, on power up it is getting only 24 mhz, there is some mysterious device on the smbus that can fix this...this code below does it. */ #define MYOUTB(val, port) movb val, %al; movw port, %dx ; outb %al, %dx #define I2C_TRANS_CMD 0x40 #define CLOCK_SLAVE_ADDRESS 0x69 MYOUTB( $0xff, $(SMBUS_IO_BASE+SMBHSTSTAT)) MYOUTB( $0x7f, $(SMBUS_IO_BASE+SMBHSTDAT0)) MYOUTB( $0x83, $(SMBUS_IO_BASE+SMBHSTCMD)) MYOUTB( $(CLOCK_SLAVE_ADDRESS<<1), $(SMBUS_IO_BASE+SMBHSTADD)) MYOUTB( $(8 | I2C_TRANS_CMD), $(SMBUS_IO_BASE+SMBHSTCTL)) movw $(SMBUS_IO_BASE+SMBHSTSTAT), %dx smbwait1: inb %dx, %al and $1, %al jnz smbwait1 ----- Now in src/mainboard/via/epia-m/Config we need to include the above file, so it ends up looking like this: mainboardinit mainboard/via/epia-m/smbusenable.inc mainboardinit superio/via/vt1211/setup_serial.inc mainboardinit pc80/serial.inc -Dave

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