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MSI 694t pro supported?
by Ben Johnson 01 Jun '04

01 Jun '04

Hi everybody, I perused through the documentation, but as I am really no specialist, I couldn't tell if Linuxbios would work with my motherboard, nor the way to put the whole thing up and running in the eventuality it would -is there any step-by-step howto for dummies like I ? The reason I ask is because the 694t's (aka 6309 v.5) bios is buggy as hell, and the kind folks at MSI do not offer support anymore. Hope not to be too much a burden on the list, my apologies if I am. Thank you for your attention, here's the output of lspci -vv: 0000:00:00.0 Host bridge: VIA Technologies, Inc. VT82C693A/694x [Apollo PRO133x] (rev c4) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ Latency: 8 Region 0: Memory at e0000000 (32-bit, prefetchable) Capabilities: [a0] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:01.0 PCI bridge: VIA Technologies, Inc. VT82C598/694x [Apollo MVP3/Pro133x AGP] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 Memory behind bridge: dde00000-dfefffff Prefetchable memory behind bridge: cdc00000-ddcfffff BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] (rev 40) Subsystem: VIA Technologies, Inc. VT82C686/A PCI to ISA Bridge Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Region 4: I/O ports at ff00 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 1a) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64, Cache Line Size: 0x08 (32 bytes) Interrupt: pin D routed to IRQ 10 Region 4: I/O ports at dc00 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.4 Bridge: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 40) Subsystem: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [68] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:0f.0 Ethernet controller: Macronix, Inc. [MXIC] MX987x5 (rev 25) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR+ FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (2000ns min, 14000ns max), Cache Line Size: 0x08 (32 bytes) Interrupt: pin A routed to IRQ 5 Region 0: I/O ports at d800 [size=dff80000] Region 1: Memory at dfffff00 (32-bit, non-prefetchable) [size=256] Expansion ROM at 00040000 [disabled] Capabilities: [44] Power Management version 1 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:10.0 Network controller: PLX Technology, Inc.: Unknown device 1151 (rev 01) Subsystem: PLX Technology, Inc.: Unknown device 1151 Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 3 Region 0: Memory at dffffe80 (32-bit, non-prefetchable) Region 1: I/O ports at d400 [size=128] Region 2: I/O ports at d000 [size=8] 0000:00:11.0 Multimedia audio controller: C-Media Electronics Inc CM8738 (rev 10) Subsystem: Hercules: Unknown device a650 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (500ns min, 6000ns max) Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at cc00 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:01:00.0 VGA compatible controller: nVidia Corporation NV11 [GeForce2 MX/MX 400] (rev a1) (prog-if 00 [VGA]) Subsystem: Asustek Computer, Inc.: Unknown device 4055 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (1250ns min, 250ns max) Interrupt: pin A routed to IRQ 11 Region 0: Memory at de000000 (32-bit, non-prefetchable) [size=dfef0000] Region 1: Memory at d0000000 (32-bit, prefetchable) [size=128M] Expansion ROM at 00010000 [disabled] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [44] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA- ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> Cheers! __________________________________ Do you Yahoo!? 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Re: Large mmio resources and 4G+ of RAM...
by YhLu 01 Jun '04

01 Jun '04

Eric, There is something called Memory lifting or memory remapping for Opteron. For example if 2G for one Opteron and two ways system. Then the CPU 0 will use [0,2G), and CPU 1 will use [4G, 6G). If the RAM for CPU is above 4G, then We must lost 1/2G for MMIO range, the reason is Opteron only has two reg for RAM LOW and HIGH limit. And there is no other regs to record the memory hole. But it seems Intel CPU has more regs to remember the memory hole. Regards YH

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Chipsets: status page?
by Joshua Wise 01 Jun '04

01 Jun '04

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I read the FAQ looking for information on chipsets supported in LinuxBIOS, and it pointed me towards the status page, however I can only find information about mainboards on that page. Am I looking in the wrong place? For reference, I'm wondering if the AMD-760 and the VIA VT82C686 are supported. Thanks, joshua - -- Joshua Wise | www.joshuawise.com GPG Key | 0xEA80E0B3 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.2 (GNU/Linux) iD8DBQFAt6GIPn9tWOqA4LMRAv+PAJ9UATxRWjvrc3RCuXSeuZlT5DuWFwCfdk8u JgBq6tZPGH9xZhz4adcmH6Y= =ndYm -----END PGP SIGNATURE-----

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Native LinuxBios Support
by Mathieu Deschamps 01 Jun '04

01 Jun '04

Hello, I've rere-reread LinuxBios port to AMD64 guide during some documentation making. I am wondering about Linuxbios Native Support and VGA init... Linuxbios is supposed to support "Trident Cyberblade 3d" natively and I have a Cyberblade/i1 rev 6a in my chipset... Please don't tell me that I've spend time making it work, though it isn't really, while there is a native support ?!? this must be a joke ! If not and that is tue and after i eat my jeans on the go, is that meaning that i've just to set CONFIG_VGABIOS and that would be all ? mathieu

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Has anyone heard about EPIA MII FastBoot ROM Utility?
by Ignacio Verona 01 Jun '04

01 Jun '04

Hi! Here http://www.viaarena.com/?PageID=343 under Booting Utility I've found what via calls FastBoot ROM. It says we can boot from PCMCIA-CompactFlash and MDOC on epia MII, and source code is provided. I'll be givin a try this week, because it will be nice to my proyect if I can boot from CF, so I can forgot about using harddisk. What do you think about? Anyone has used this?

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Re: Greetings
by Hendricks David W. 29 May '04

29 May '04

Welcome! Did you have anything specific in mind? A specific mainboard that you want to work on, perhaps? On Fri, 28 May 2004 jcantara(a)comcast.net wrote: > Hello, > > I'm new to: This List, and Linux in general. > > Why I joined: I have a keen interest in both Linux and BIOSs, and may be able to provide some help on the BIOS and hardware end of things. > > Some about me: I work for a company that provides "aftermarket" Award BIOSs, built from source provided to us through an agreement with Award themselves. I'm a semi-recent graduate of Electrical Engineering, and live in Massachusetts. I actually concentrated in embedded systems design, but I ended up here, configuring BIOSs, and working on the company website, go figure :) > > I thought I might be able to provide some help on the hardware side of things, having a lot of insight into the BIOS. Obviously I can't share the source code we have, or violate any of the agreements my company has though. > > This list seems fairly busy, from the few mails I've already received today since I signed up. > > -Jesse > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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testbios: other chips?
by Joshua Wise 29 May '04

29 May '04

I've seen various success stories of testbios being used to execute VGA BIOSes and get VGA cards running. This led me to ask the question of whether it would be feasible to get BIOSes from other option cards, such as my "00:13.0 Unknown mass storage controller: Triones Technologies, Inc. HPT366/368/370/370A/372 (rev 04)" to execute and initialize. Thanks, joshua -- Joshua Wise | www.joshuawise.com GPG Key | 0xEA80E0B3

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Know someone available for a freebios port to an SMP Opteron motherboard? (fwd)
by Hendricks David W. 28 May '04

28 May '04

Any takers? ---------- Forwarded message ---------- Date: Fri, 28 May 2004 13:52:18 -0700 From: William J. Earl <earl(a)agami.com> To: ollie(a)users.sourceforge.net, ebiederm(a)users.sourceforge.net, dhendricks(a)users.sourceforge.net Subject: Know someone available for a freebios port to an SMP Opteron motherboard? I am working with freebios for an SMP Opteron motherboard, but I am very new to the source base. Would you know of anyone who might be available for a short contract to configure and bring up freebios on a new Opteron motherboard? I have the relevant documentation and the cooperation of the vendor, and working boards. I am writing to you as you have recently been checking in improvements to freebios for Opteron.

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答复: 答复: 答复: 答复: Getting Started with freebios2!
by YhLu 28 May '04

28 May '04

You got time for USB boot debug? Do you have any idea about: USB device control ed works well, but the bulk ed doesn't work, USB report device not responding? Does the code in baremetal work? In the code, signature of cbw and csw define missed 0x. Regards YH -----邮件原件----- 发件人: Steven James [mailto:pyro@linuxlabs.com] 发送时间: 2004年5月27日 15:56 收件人: YhLu 抄送: ron minnich; Jay Miller; ebiederman(a)lnxi.com; LinuxBIOS 主题: Re: 答复: 答复: 答复: Getting Started with freebios2! Greetings, I'm finally getting dug out after being snowed under :-) The spec is probably part of: http://www.usb.org/developers/devclass_docs/usbcdc11.pdf The communications class. I'm guessing it would be a subset of POTS modem with a transparent data protocol. That would imply line contol on the control ep, and either bulk transfer or isochronous pipe pairs for the serial data. It's a lot more involved than a simple UART, that's for sure. On a side note, I THOUGHT I would have time by now to bang on the USB boot. Hopefully, I'll be able to do more with it now (so I say :-) As soon as I get up to speed on freebios2, I'll have a good test platform. For the serial, UHCI and OHCI will be good. EHCI can likely be ignored for the BIOS since fast devices are required to fall back and EHCI always has one of UHCI or OHCI to handle low speed USB. G'day, sjames -------------------------steven james, director of research, linux labs ... ........ ..... .... 230 peachtree st nw ste 2701 the original linux labs atlanta.ga.us 30303 -since 1995 http://www.linuxlabs.com office & fax 866.545.6306 ----------------------------------------------------------------------- On Thu, 27 May 2004, YhLu wrote: > So the LinuxBIOS need to > 1. init USB controller > 2. create usb_dev to be serial. > 3. use usb_control_msg and usb_bulk_msg to talk with the serial device. > > What the USB type, OHCI or UCHI or EHCI?? > > I wonder if some source code or documents that define No 3 above? > > Regards > > YH > > -----邮件原件----- > 发件人: ron minnich [mailto:rminnich@lanl.gov] > 发送时间: 2004年5月27日 14:23 > 收件人: YhLu > 抄送: Jay Miller; ebiederman(a)lnxi.com; LinuxBIOS > 主题: Re: 答复: 答复: Getting Started with freebios2! > > On Thu, 27 May 2004, YhLu wrote: > > > Usb to serial ??? > > yes, it's now needed :-( > > ron > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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答复: 答复: [COMMIT] romcc 0.63 and some fixes...
by YhLu 28 May '04

28 May '04

After I get USB boot done, I will try that and modify the auto.c..... Regards YH -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2004年5月28日 9:56 收件人: YhLu 抄送: LinuxBIOS 主题: Re: 答复: [COMMIT] romcc 0.63 and some fixes... YhLu <YhLu(a)tyan.com> writes: > I'd like to wait it to produce smaller code. Otherwise if I enable superio + > ati support, It will be greater than 64K in debug mode. > > When will that be ready? The code is feature complete so it will correctly not inline functions (producing smaller code) if it does not run out of registers. My simple test cases have worked well. My complicated test case that uses an old version of production code ran out of registers after consuming just the 8 general purpose registers. So mostly it is a matter of playing with the code, and figuring out why weird things are happening. Eric

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