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39713 discussions

pnp_enable_resource not being called
by Greg Watson 24 Nov '04

24 Nov '04

The sandpoint has the following structure: Northbridge MPC107 --> Southbridge W83C553 --> Superio PC97307 The config file looks like: chip northbridge/motorola/mpc107 device pci_domain 0 on device pci 0.0 on end device pci b.0 on chip southbridge/winbond/w83c553 chip superio/NSC/pc97307 device pnp 15c.0 on end # Kyeboard device pnp 15c.1 on end # Mouse device pnp 15c.2 on end # Real-time Cloc k device pnp 15c.3 on end # Floppy device pnp 15c.4 on end # Parallel port device pnp 15c.5 on end # com2 device pnp 15c.6 on end # com1 device pnp 15c.7 on end # gpio device pnp 15c.8 on end # Power manageme nt end end end # pci to isa bridge device pci b.1 on end # pci ide controller end device cpu_bus 0 on chip cpu/ppc/mpc74xx device cpu 0 on end end end end The dev_enumerate() code is calling the PNP enable routines and the dev_initialize() code is calling the PNP init routine. However the dev_enable() code never calls the PNP enable_resource routine, which means the the PNP devices are never actually enabled. The enable_dev routine for the superio device calls: pnp_enable_devices(dev, &ops, sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); where ops is defined as: static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, }; Any ideas why this is not working? Is there something else that needs to happen? Greg

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RE: 4G 4 Rank memory module
by YhLu 24 Nov '04

24 Nov '04

Repeat the i2c address two times make the memory modules fail. At that case some thing being done twice...cause that... YH -----Original Message----- From: YhLu Sent: Wednesday, November 24, 2004 10:44 AM To: ebiederman(a)lnxi.com Cc: Stefan Reinauer; 'LinuxBIOS' Subject: RE: 4G 4 Rank memory module Eric, Our MB all CS are connected. DIMM0 and DIMM1 are using 0, 1, 4, 5. DIMM2 and DIMM3 are using 2, 3, 6, 7. Then need to change to static const struct mem_controller cpu[] = { { .node_id = 0, .f0 = PCI_DEV(0, 0x18, 0), .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), .channel0 = { (0xa<<3)|0, (0xa<<3)|2, (0xa<<3)|0, (0xa<<3)|2, }, .channel1 = { (0xa<<3)|1, (0xa<<3)|3, (0xa<<3)|1, (0xa<<3)|3, }, }, Regards YH -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Wednesday, November 24, 2004 12:55 AM To: YhLu Cc: Stefan Reinauer; 'LinuxBIOS' Subject: Re: 4G 4 Rank memory module YhLu <YhLu(a)tyan.com> writes: > It can treat 4G as 2G modules, if I comment out physical bank check. (!=2 > get out). Ah so it is the explicit check for <= 2 Ranks that is the immediate problem :) This case is peculiar enough I did not add support because I could not test it. Does your board have 4 chip selects running to the dimm socket? If not you cannot support 4 rank dimms. What does your struct mem_controller look like? One partial solution would be to simply repeat the spd address twice in the channel structure, and comment out the maximum bank check. Of course that would fail for non quad rank dimms. So I am not quite certain what the complete solution is. YhLu once you describe how your dimm sockets are wired we can figure something out. static const struct mem_controller cpu[] = { { .node_id = 0, .f0 = PCI_DEV(0, 0x18, 0), .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, }, Eric _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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linuxbios vs award bios on EPIA-M
by Dave Ashley 24 Nov '04

24 Nov '04

The VIA XFree86 module for CLE266 used on the epia-m makes some assumptions about certain of the VGA registers containing information that would have been set by the bios. Specifically here is a code snippet from XFree86 4.3.0: /* Next go on to detect amount of installed ram */ if (pScrn->videoRam < 16384 || pScrn->videoRam > 65536) { bMemSize = BIOS_GetVideoMemSize(pScrn); if (bMemSize) { pScrn->videoRam = bMemSize << 6; } else { VGAOUT8(0x3C4, 0x39); bMemSize = VGAIN8(0x3c5); if (bMemSize > 16 && bMemSize <= 128) { pScrn->videoRam = (bMemSize + 1) << 9; } else if (bMemSize > 0 && bMemSize < 31){ pScrn->videoRam = bMemSize << 12; } else { DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "bMemSize = %d\nGet Video Memory Size by default.\n", bMemSize)); pScrn->videoRam = VIAGetMemSize(); } } } And here is from XFree86 4.4.0: /* detect amount of installed ram */ if (pScrn->videoRam < 16384 || pScrn->videoRam > 65536) { if(pVia->Chipset == VIA_CLE266) bMemSize = hwp->readSeq(hwp, 0x34); else bMemSize = hwp->readSeq(hwp, 0x39); if (bMemSize > 16 && bMemSize <= 128) pScrn->videoRam = (bMemSize + 1) << 9; else if (bMemSize > 0 && bMemSize < 31) pScrn->videoRam = bMemSize << 12; else { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Memory size detection failed: using 16MB\n"); pScrn->videoRam = 16 << 10; /* Assume the base 16Mb */ } } So the older version tries to query the BIOS first. The newer version doesn't even bother with the bios and assumes the VGA Seq registers 0x39 or 0x34 contain the memory size. 3c5.34 is Scratch Pad Register 3 3c5.39 is BIOS reserved register 0 XF4.4.0 seems to abstract how the VGA sequence registers are accessed. Even the logic seems strange, XF4.3.0 assumes seq 0x39 has the info, but XF4.4.0 assumes seq 0x39 has the info. linuxbios isn't initializing either as far as I know. To handle this safely it would seem it must set the ram size in both seq registers. This seems really weird, using vga seq scratch registers to convey information from the BIOS to XFree86. Is this common or something specific to VIA? -Dave

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RE: 4G 4 Rank memory module
by YhLu 24 Nov '04

24 Nov '04

Eric, Our MB all CS are connected. DIMM0 and DIMM1 are using 0, 1, 4, 5. DIMM2 and DIMM3 are using 2, 3, 6, 7. Then need to change to static const struct mem_controller cpu[] = { { .node_id = 0, .f0 = PCI_DEV(0, 0x18, 0), .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), .channel0 = { (0xa<<3)|0, (0xa<<3)|2, (0xa<<3)|0, (0xa<<3)|2, }, .channel1 = { (0xa<<3)|1, (0xa<<3)|3, (0xa<<3)|1, (0xa<<3)|3, }, }, Regards YH -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Wednesday, November 24, 2004 12:55 AM To: YhLu Cc: Stefan Reinauer; 'LinuxBIOS' Subject: Re: 4G 4 Rank memory module YhLu <YhLu(a)tyan.com> writes: > It can treat 4G as 2G modules, if I comment out physical bank check. (!=2 > get out). Ah so it is the explicit check for <= 2 Ranks that is the immediate problem :) This case is peculiar enough I did not add support because I could not test it. Does your board have 4 chip selects running to the dimm socket? If not you cannot support 4 rank dimms. What does your struct mem_controller look like? One partial solution would be to simply repeat the spd address twice in the channel structure, and comment out the maximum bank check. Of course that would fail for non quad rank dimms. So I am not quite certain what the complete solution is. YhLu once you describe how your dimm sockets are wired we can figure something out. static const struct mem_controller cpu[] = { { .node_id = 0, .f0 = PCI_DEV(0, 0x18, 0), .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, }, Eric

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Resource base 0x1xy for AMD K8 northbridge.
by Li-Ta Lo 24 Nov '04

24 Nov '04

Eric, Why you add 0x100 to the resource base register for AMDK8 Function 1, in find_mem|io_pair()? if (reg > 0) { resource = new_resource(dev, 0x100 + (reg | link)); } Ollie

2 2

Heterogeneous clusters with Clustermatic
by Reza Shahidi 24 Nov '04

24 Nov '04

Hello all: I just wanted to see if Clustermatic supports heterogeneous clusters. We have 4 identical slave nodes for the time being, but we may want to add some more machines later on. This has probably been answered in the documentation somewhere, but I haven't been able to find it. I hope I am E-mailing the correct list. Thanks, Reza

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RE: [Etherboot-users] Direct message to com2
by YhLu 24 Nov '04

24 Nov '04

It seems that mkelfImage should get the com address from commandline. For example: mkelfImage --command-line="ramdisk_size=65536 root=/dev/ram0 rw console=tty0 console=ttyS1,115200n8" --kernel=linuxkernel/bzImage_2. 6.9_k8.2 --ramdisk=rootfs/mydisk8_com2.gz --output=elf/ram0_2.5_2.6.9_k8.2_mydisk8_com2.elf Then makeelfImage should use 0x2f8 instead of 0x3f8 in convert_params.c according to ttyS1. Regards YH -----Original Message----- From: YhLu Sent: Monday, November 22, 2004 6:20 PM To: YhLu; ebiederman(a)lnxi.com Cc: linuxbios(a)clustermatic.org; etherboot-users(a)lists.sourceforge.net Subject: RE: [Etherboot-users] Direct message to com2 It's in mkelfImage 2.5 linux-i386/ convert_params.c it is hardcode to 0x3f8. YH -----Original Message----- From: YhLu Sent: Monday, November 22, 2004 6:05 PM To: ebiederman(a)lnxi.com Cc: linuxbios(a)clustermatic.org; etherboot-users(a)lists.sourceforge.net Subject: RE: [Etherboot-users] Direct message to com2 Eric, I add second serial_x.c to support com2. then it works well. The "Firmware type: LinuxBIOS" only comes out in COM1. Which segement print " Firmware type: LinuxBIOS" ?, it seems hardcoded to use 0x3f8. Regards YH -----Original Message----- From: YhLu Sent: Monday, November 22, 2004 3:04 PM To: linuxbios(a)clustermatic.org; ebiederman(a)lnxi.com; etherboot-users(a)lists.sourceforge.net Subject: [Etherboot-users] Direct message to com2 Who has met such problem? I changed the linuxbios to direct message to com2 via changing 1. SP1 to SP2 in auto.c 2. enable com2 in Config.lb 3. change 0x3f8 to 0x2f8 in Options.lb Etherboot change 0x3f8 to 0x2f8. Then After Ethertboot get the elf image from tftp server, it will hang a while (30s) at "Firmware type: LinuxBIOS", and that message is not shown. I remember several months ago, when I make message comes to both ports (COM1 and COM2), it worked well.... Weird. Regards YH [tg3-5703X]Ethernet addr: 00:E0:81:27:2D:30 Tigon3 [partno(BCM95703A30) rev 1002 PHY(5703)] (PCIX:100MHz:64-bit) Link is up at 1000 Mbps, full duplex. TX RX flow control Searching for server (DHCP)... ..Me: 192.168.1.191, Server: 192.168.1.1, Gateway 192.168.1.1 Loading 192.168.1.1:ram0_2.5_2.6.9_k8.2_mydisk8_com2.elf ...(ELF)... ............................................................... ....................................................... ............................................................................ ...............................................done (Firmware type: LinuxBIOS) old bootloader convention, maybe loadlin? Bootdata ok (command line is root=/dev/ram0 rw console=ttyS0,115200n8 ) Linux version 2.6.9 (root@tst288xsuse9) (gcc version 3.3.3 (SuSE Linux)) #15 SMP Mon Nov 22 14:53:36 PST 2004 ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real users. Discover which products truly live up to the hype. Start reading now. http://productguide.itmanagersjournal.com/ _______________________________________________ Etherboot-users mailing list Etherboot-users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/etherboot-users ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real users. Discover which products truly live up to the hype. Start reading now. http://productguide.itmanagersjournal.com/ _______________________________________________ Etherboot-users mailing list Etherboot-users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/etherboot-users

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Compile error
by Adam Talbot 24 Nov '04

24 Nov '04

Any ideas on this error? What is causing theis? /root/freebios2/src/mainboard/commell/lv-671/auto.c -o auto.inc raminit.c:1369.39: member channel1 not present make[1]: *** [auto.inc] Error 1 make[1]: Leaving directory `/root/linuxbios/lv-671.512kflash/normal' make: *** [normal/linuxbios.rom] Error 1 -Adam Talbot

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RE: 4G 4 Rank memory module
by YhLu 24 Nov '04

24 Nov '04

It can treat 4G as 2G modules, if I comment out physical bank check. (!=2 get out). YH -----Original Message----- From: Stefan Reinauer [mailto:stepan@openbios.org] Sent: Tuesday, November 23, 2004 1:03 PM To: YhLu Cc: 'Eric W. Biederman'; 'LinuxBIOS' Subject: Re: 4G 4 Rank memory module * YhLu <YhLu(a)tyan.com> [041123 22:04]: > 2G modules for CPU0 It seems to dislike the 2G Modules it seems..? Can you try with only the 4G modules? > 4G modules for CPU1. > > -----Original Message----- > From: Stefan Reinauer [mailto:stepan@openbios.org] > Sent: Tuesday, November 23, 2004 12:56 PM > To: YhLu > Cc: 'Eric W. Biederman'; 'LinuxBIOS' > Subject: Re: 4G 4 Rank memory module > > * YhLu <YhLu(a)tyan.com> [041123 20:51]: > > Ram2.00 > > rows: 0x0000000d > > columns: 0x0000000c > > banks: 0x00000004 > > module data width : 0x00000048 > > side2 banks: 0x00000002 > > > Ram2.01 > > rows: 0x0000000d > > columns: 0x0000000c > > banks: 0x00000004 > > module data width : 0x00000048 > > side2 banks: 0x00000004 > > Bad SPD value > > > > CPU0 got 2G modules > > CPU1 got 4G modules > > Side2 banks is different. > > Is this with two different modules? Ram2.00 Shows a difference. > Maybe noise on the I2C bus? Ram2.01 seems to be ok..?!? > > Stefan >

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RE: 4G 4 Rank memory module
by YhLu 23 Nov '04

23 Nov '04

2G modules for CPU0 4G modules for CPU1. -----Original Message----- From: Stefan Reinauer [mailto:stepan@openbios.org] Sent: Tuesday, November 23, 2004 12:56 PM To: YhLu Cc: 'Eric W. Biederman'; 'LinuxBIOS' Subject: Re: 4G 4 Rank memory module * YhLu <YhLu(a)tyan.com> [041123 20:51]: > Ram2.00 > rows: 0x0000000d > columns: 0x0000000c > banks: 0x00000004 > module data width : 0x00000048 > side2 banks: 0x00000002 > Ram2.01 > rows: 0x0000000d > columns: 0x0000000c > banks: 0x00000004 > module data width : 0x00000048 > side2 banks: 0x00000004 > Bad SPD value > > CPU0 got 2G modules > CPU1 got 4G modules > Side2 banks is different. Is this with two different modules? Ram2.00 Shows a difference. Maybe noise on the I2C bus? Ram2.01 seems to be ok..?!? Stefan

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