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[LinuxBIOS] The actual location for Open Solaris has been announced
by Gregg C Levine 16 Jun '05

16 Jun '05

Hello from Gregg C Levine I have news regarding Open Solaris. It now lives at http://opensolaris.org The one posted earlier is now probably closed. The announcement was dated the 14th. It came to my other e-mail ID, today. --- Gregg C Levine hansolofalcon(a)worldnet.att.net --- "The Force will be with you... Always." Obi-Wan Kenobi

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[LinuxBIOS] S2735 tree is totall broken
by YhLu 16 Jun '05

16 Jun '05

with romcc, also there is a werid reset, in raminit stage LinuxBIOS-1.1.8_s2735_Fallback Thu Jun 16 19:15:24 PDT 2005 starting... SMBus controller enabled Ram1.00 Ram2.00 Ram3 LinuxBIOS-1.1.8_s2735_Fallback Thu Jun 16 19:15:24 PDT 2005 starting... SMBus controller enabled Ram1.00 Ram2.00 Ram3 Ram4 PCI: 00:00.00 00: 86 80 4c 25 06 00 90 00 01 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 11 00 00 00 00 00 00 00 00 00 00 00 00 50: 04 60 0d 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 10 20 30 40 50 60 60 60 00 00 00 00 00 00 00 00 70: 44 44 44 00 00 00 00 00 1f 02 01 39 79 02 67 20 80: b1 0b 71 00 00 00 00 00 00 98 10 d2 88 00 00 00 90: 00 00 00 00 00 00 00 00 55 05 55 05 01 02 38 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 11 00 c0 60 00 70 00 00 00 00 00 00 00 d0: 02 28 00 0e 03 00 00 33 80 09 31 b5 00 00 00 00 e0: 1c 1d 00 00 00 00 00 00 58 44 00 00 00 00 00 00 f0: 00 00 00 00 76 00 30 40 40 0f 00 00 00 00 00 00 Done. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.8_s2735_Fallback Thu Jun 16 19:15:24 PDT 2005 booting... clocks_per_usec: 4538 Enumerating buses... PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled done Allocating resources... Reading resources... PCI_DOMAIN: 0000 missing read_resources APIC_CLUSTER: 0 missing read_resources PCI_DOMAIN: 0000 missing read_resources APIC_CLUSTER: 0 missing read_resources Done reading resources. Setting resources... PCI_DOMAIN: 0000 missing read_resources APIC_CLUSTER: 0 missing read_resources PCI_DOMAIN: 0000 missing read_resources APIC_CLUSTER: 0 missing read_resources Done setting resources. Done allocating resources. Enabling resourcess... PCI_DOMAIN: 0000 missing enable_resources APIC_CLUSTER: 0 missing enable_resources done. Initializing devices... Root Device init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... Inconsistent IRQ routing table size (0xd0/0x110) check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 /home/yhlu/xx/xx/freebios2/src/arch/i386/boot/pirq_routing.c: 36:check_pirq_routing_table() - checksum is: 0x91 but should be: 0a done. Wrote the mp table end at: 00000020 - 000001e4 Wrote linuxbios table at: 00000500 - 00000b9c checksum 56e5 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3

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RE: [LinuxBIOS] Solaris
by YhLu 15 Jun '05

15 Jun '05

SUN visit us some time, but i'm not interested in that, so i didn't attend that meeting..... YH > -----Original Message----- > From: Gregg C Levine [mailto:hansolofalcon@worldnet.att.net] > Sent: Wednesday, June 15, 2005 11:16 AM > To: 'yhlu'; 'Justin Cormack' > Cc: linuxbios(a)openbios.org > Subject: RE: [LinuxBIOS] Solaris > > Hello from Gregg C Levine > Funny you should be asking that question. > At an event the company called "Boot Camp", they displayed > laptops running Opterons, and Solaris, via the AMD64 code. I > have here several copies of X86, and SPARC Solaris products. > Currently there is default support for AMD64 based systems > including their own boxes. This is all via Solaris 10. > ---- > Gregg C Levine hansolofalcon(a)worldnet.att.net > --- > "The Force will be with you... Always." Obi-Wan Kenobi > > > -----Original Message----- > > From: linuxbios-bounces(a)openbios.org > [mailto:linuxbios-bounces@openbios.org] > > On Behalf Of yhlu > > Sent: Wednesday, June 15, 2005 1:48 PM > > To: Justin Cormack > > Cc: linuxbios(a)openbios.org > > Subject: Re: [LinuxBIOS] Solaris > > > > I guess LinuxBIOS+OpenBIOS could help. > > > > which solaris version? > > > > Is there special solaris version support Opteron in 64bit? > > > > YH > > > > On 15 Jun 2005 18:12:36 +0000, Justin Cormack > <justin(a)street-vision.com> wrote: > > > > > > > > > Has anyone looked at what it would take to get Solaris booting > under > > > Linuxbios on Opteron? > > > > > > If not I might dig around (there is a modified grub - I think that > does > > > some of the init work; one suspects that because of its heritage > it is > > > quite BIOS-unencumbered). > > > > > > justin > > > > > > > > > > > > > > > _______________________________________________ > > > LinuxBIOS mailing list > > > LinuxBIOS(a)openbios.org > > > http://www.openbios.org/mailman/listinfo/linuxbios > > > > > > > _______________________________________________ > > LinuxBIOS mailing list > > LinuxBIOS(a)openbios.org > > http://www.openbios.org/mailman/listinfo/linuxbios > > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

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[LinuxBIOS] Errror messages for sending e-mail
by Gregg C Levine 15 Jun '05

15 Jun '05

Hello from Gregg C. Levine Justin regarding that posting you made earlier. I just tried sending you my response, regarding Solaris, and our work. Both were sent via the private e-mail method, and the list. The list worked. The private method failed, with a complaint. The complaint was: 'Justin Cormack' on 6/15/05 2:17 PM 450 [TEMPFAIL] destination not valid within DNS I suspect this is a temporary issue, but please e-mail me directly to confirm otherwise. ---- Gregg C Levine hansolofalcon(a)worldnet.att.net --- "The Force will be with you... Always." Obi-Wan Kenobi

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[LinuxBIOS] CN400 support
by Dave Ashley 15 Jun '05

15 Jun '05

VIA's released the EPIA-SP and they're in production, they've got the CN400 northbridge, VT8237 southbridge. Has anyone tried linuxbios on one of these? -Dave

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RE: [BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram.
by YhLu 14 Jun '05

14 Jun '05

AMD cache_as_ram first stage done. current status 1. use gcc to produce auto.inc or init.o 2. it can reboot in fallback 3. it can reboot from fallback to normal 4. it can reboot in normal.... I'm using auto.c for romcc version cache_as_ram_auto.c for gcc and via auto.inc version cache_as_ram_auto.c for gcc and via init.o version next stage: 1. convert cache_as_ram_init.c version. 2. it will use the printk_debug to substitue print_debug 3. create compressed init.o version???? could spare 10k bytes.... YH

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[LinuxBIOS] E7501 SDRAM command bug?
by Steven J. Magnani 14 Jun '05

14 Jun '05

I'm still working on getting the DRAM running on our E7501-based board. I've run across something in the E7501 raminit code that doesn't look right. The E7501 datasheet isn't clear about how RAM commands get sent to the DIMMs. All it says is (for example): "NOP Command Enable - All processor cycles to DRAM result in a NOP command on the DRAM interface". It isn't clear whether a single access to DRAM causes the command to go to all DIMMs, or only to the one addressed by the access. I ran some experiments and it appears that only the addressed DIMM gets the command. So, the raminit.c code that sends commands to RAM (below) needs to loop over all the possible DIMMs, accessing a memory address that lies within each. static inline void do_ram_command (const struct mem_controller *ctrl, uint32_t value) { uint32_t dword; uint8_t byte; int i; uint32_t result; /* Compute the offset */ dword = value >> 16; for(i=0;i<8;i++) { /* Set the ram command */ byte = pci_read_config8(ctrl->d0, 0x7c); byte &= 0x8f; byte |= (uint8_t)(value & 0xff); pci_write_config8(ctrl->d0, 0x7c, byte); /* Assert the command to the memory */ result = read32(dword); /* Go to the next base address */ dword += 0x04000000; } /* The command has been sent to all dimms so get out */ } The problem is that the code assumes that the address "distance" from one DIMM to the next is always 0x04000000. Depending on the DIMM geometry, that may not be the case. Instead, shouldn't the code be using the previously-initialized DRAM boundary registers to construct addresses for each DIMM? And for systems with more than 4 GB, shouldn't it have the ability to access 36-bit addresses? Steve Magnani www.digidescorp.com

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RE: [LinuxBIOS] E7501 SDRAM timing bug?
by YhLu 14 Jun '05

14 Jun '05

Good, Can you compare the raminit.inc in V1, and raminit.c in V2? So make sure if my translation cause problm. Thanks YH > -----Original Message----- > From: Steven J. Magnani [mailto:steve@digidescorp.com] > Sent: Tuesday, June 14, 2005 10:33 AM > To: 'Ronald G. Minnich' > Cc: linuxbios(a)openbios.org > Subject: [LinuxBIOS] E7501 SDRAM timing bug? > > Another suspicious looking bit of E7501 RAM initialization code...in > spd_set_dram_controller_mode() there is code that reads the > SPD address/command hold time and configures the E7501 for > "1n rule" or "2n rule" operation: > > value = spd_read_byte(ctrl->channel0[i], 33); > /* Address and command hold time after clock */ > if(value < 0) continue; > if(value >= 0xa0) { /* At 133Mhz this > constant should be 0x75 */ > dword &= ~(1<<16); /* Use two clock cyles > instead of one */ > } > > The issues here are frequency and scale. > > The rest of the E7501 code assumes 133 MHz operation. So it > looks from the comments like the comparison to 0xa0 should > really be to 0x75. > > But the SPD value is in _tenths_ of nanoseconds. So the above > code translates to, "if the address/hold time is more than 1 > ns, use 2 clock cycles per command". But the clock period is > 10 ns for 100 MHz or 7.5 ns for 133 MHz, which is an order of > magnitude larger than the SPD values. > > I didn't see code for any other chipset that did something > like this, except the Intel 855pm - where it's #ifdef'd out. > I'm thinking this code should be removed. > > Steve > www.digidescorp.com > > > > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

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RE: [BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram.
by YhLu 13 Jun '05

13 Jun '05

Get into hardwaremain now, and boot_complete is right, but the console_init cause cpu_reset...... YH void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; post_code(0x80); /* displayinit MUST PRECEDE ALL PRINTK! */ console_init();

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RE: [BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram.
by YhLu 13 Jun '05

13 Jun '05

I got the stack in ram works. it when execute the dump_mem(dst, dst+0x100); print_debug("Jumping to LinuxBIOS.\r\n"); __asm__ volatile ( "cli\n\t" "leal _iseg, %edi\n\t" "jmp %edi\n\t" ); in copy_and_run.c, the jmp will cause cpu_reset.... It's strang.... I want to check in the cache_as_ram code, and it can coexist with old romcc code, ( by USE_DCACHE_RAM to switch..) Please let me know if you want to check that code in...... YH LinuxBIOS-1.1.8_s2891_Fallback Mon Jun 13 14:33:38 PDT 2005 starting... (0,1) link=01 (1,0) link=00 02 nodes initialized. SBLink=00 NC node|link=00 NC node|link=02 busn=06 ht reset - LinuxBIOS-1.1.8_s2891_Fallback Mon Jun 13 14:33:38 PDT 2005 starting... (0,1) link=01 (1,0) link=00 02 nodes initialized. SBLink=00 NC node|link=00 NC node|link=02 busn=06 SMBus controller enabled Ram1.00 Ram1.01 Ram2.00 Ram2.01 Ram3 Initializing memory: done Initializing memory: done Ram4 v_esp=000cfe84 Clearing initial memory region: No cache as ram now - Use Ram as Stack now - done Copying LinuxBIOS to ram. src=fffe9c84 dst=00004000 0x00004000: fa 2e 0f 01 15 31 41 00 00 ea 10 40 00 00 10 00 0x00004010: b8 18 00 00 00 8e d8 8e c0 8e d0 8e e0 8e e8 b0 0x00004020: 13 e6 80 8d 3d 00 e0 03 00 b9 00 60 04 00 29 f9 0x00004030: 31 c0 f3 aa 8d 3d 70 54 02 00 b9 e8 dd 03 00 29 0x00004040: f9 74 04 31 c0 f3 aa bc 00 60 04 00 6a 00 6a 00 0x00004050: 55 89 e5 8d 3d 10 ad 01 00 8d 1d 9a 40 00 00 b8 0x00004060: 00 00 10 00 66 89 d8 89 da 66 ba 00 8e 89 47 00 0x00004070: 89 57 04 83 c3 06 83 c7 08 81 ff b0 ad 01 00 75 0x00004080: e3 0f 01 1d 08 ad 01 00 b0 fe e6 80 89 ec e8 a5 0x00004090: 42 00 00 b0 ee e6 80 f4 eb f9 6a 00 6a 00 eb 72 0x000040a0: 6a 00 6a 01 eb 6c 6a 00 6a 02 eb 66 6a 00 6a 03 0x000040b0: eb 60 6a 00 6a 04 eb 5a 6a 00 6a 05 eb 54 6a 00 0x000040c0: 6a 06 eb 4e 6a 00 6a 07 eb 48 6a 08 eb 44 90 90 0x000040d0: 6a 00 6a 09 eb 3c 6a 0a eb 38 90 90 6a 0b eb 32 0x000040e0: 90 90 6a 0c eb 2c 90 90 6a 0d eb 26 90 90 6a 0e 0x000040f0: eb 20 90 90 6a 00 6a 0f eb 18 6a 00 6a 10 eb 12 Jumping to LinuxBIOS. Clearing initial memory region: No cache as ram now - Use Ram as Stack now - done Copying LinuxBIOS to ram. src=fffe9c84 dst=00004000 0x00004000: fa 2e 0f 01 15 31 41 00 00 ea 10 40 00 00 10 00 0x00004010: b8 18 00 00 00 8e d8 8e c0 8e d0 8e e0 8e e8 b0 0x00004020: 13 e6 80 8d 3d 00 e0 03 00 b9 00 60 04 00 29 f9 0x00004030: 31 c0 f3 aa 8d 3d 70 54 02 00 b9 e8 dd 03 00 29 0x00004040: f9 74 04 31 c0 f3 aa bc 00 60 04 00 6a 00 6a 00 0x00004050: 55 89 e5 8d 3d 10 ad 01 00 8d 1d 9a 40 00 00 b8 0x00004060: 00 00 10 00 66 89 d8 89 da 66 ba 00 8e 89 47 00 0x00004070: 89 57 04 83 c3 06 83 c7 08 81 ff b0 ad 01 00 75 0x00004080: e3 0f 01 1d 08 ad 01 00 b0 fe e6 80 89 ec e8 a5 0x00004090: 42 00 00 b0 ee e6 80 f4 eb f9 6a 00 6a 00 eb 72 0x000040a0: 6a 00 6a 01 eb 6c 6a 00 6a 02 eb 66 6a 00 6a 03 0x000040b0: eb 60 6a 00 6a 04 eb 5a 6a 00 6a 05 eb 54 6a 00 0x000040c0: 6a 06 eb 4e 6a 00 6a 07 eb 48 6a 08 eb 44 90 90 0x000040d0: 6a 00 6a 09 eb 3c 6a 0a eb 38 90 90 6a 0b eb 32 0x000040e0: 90 90 6a 0c eb 2c 90 90 6a 0d eb 26 90 90 6a 0e 0x000040f0: eb 20 90 90 6a 00 6a 0f eb 18 6a 00 6a 10 eb 12 Jumping to LinuxBIOS. Clearing initial memory region: No cache as ram now - Use Ram as Stack now - done Copying LinuxBIOS to ram. src=fffe9c84 dst=00004000

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