coreboot August 2024

coreboot@coreboot.org

12 participants
28 discussions

Announcement: Introducing UEFI Capsule Update Integration for coreboot with EDK II
by Beata Skierka 14 Sep '24

14 Sep '24

Hello, We are pleased to announce the launch of a project by 3mdeb aimed at integrating UEFI Capsule Update for coreboot with EDK II as a payload. This initiative aims to bring the capsule-based update method, providing an alternative to the traditional flashrom-based method, which becomes more and more difficult to implement, due to the restricted OS-level access to the firmware storage. One of the main goals is also to ease the integration and firmware update deployments via the fwupd for devices running open-source firmware (based on coreboot + EDK II). For a detailed project outline, please visit our Dasharo documentation [1]. We are looking for feedback through comments on this thread or via the built-in discussion module on the website. Although the project plan has been already accepted by the NLnet Foundation, there may be still some room for justified changes. You can track project's progress via the GitHub Project [2]. Your feedback and participation would be much appreciated. We welcome your involvement in discussions, reviewing, and testing. You might already have seen some first patches as a results of this project getting started, such us: - https://review.coreboot.org/c/coreboot/+/82247 - https://review.coreboot.org/c/coreboot/+/82248 - https://review.coreboot.org/c/coreboot/+/82249 - https://review.coreboot.org/c/coreboot/+/82610 We acknowledge and appreciate the funding support from the NLnet Foundation. [1] https://docs.dasharo.com/projects/capsule-updates/ [2] https://github.com/orgs/Dasharo/projects/7/views/1 Best regards, Beata Skierka Project Manager https://3mdeb.com | @3mdeb_com

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Gerrit Gitiles is back - for now
by Felix Singer 10 Sep '24

10 Sep '24

I've just enabled Gitiles again. We will observe which effect this has on Gerrit now. Fingers crossing that it won't cause a high load anymore :) Felix

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[coreboot - Bug #548] (New) Computer Fails To Recognize Upgraded WiFi Card
by Jeremy Brown 02 Sep '24

02 Sep '24

Issue #548 has been reported by Jeremy Brown. ---------------------------------------- Bug #548: Computer Fails To Recognize Upgraded WiFi Card https://ticket.coreboot.org/issues/548 * Author: Jeremy Brown * Status: New * Priority: Normal * Target version: none * Start date: 2024-07-15 ---------------------------------------- I am running coreboot 24.05 on my Lenovo X201. I decided to upgrade my WiFi card from an Intel Centrino Advanced-N 6205 to an Intel Wireless-AC 7260; since I selected the option to support Intel PCIe cards in my build config I expected everything to work but my computer fails to recognize the new card. The old card is still recognized if I reinstall it so I know I didn't mess up the socket somehow; I've read reports of the 7260 [working with a modded factory BIOS](https://richbits.rbarnes.org/installing-the-intel-7260-in-the-thinkpa… so I don't think there's an electrical issue. I've attached lspci data from both chips, lmk if additional information is needed. ---Files-------------------------------- 6205_lspci_tree.txt (1.63 KB) 7260_lspci_tree.txt (1.57 KB) 6205_lspci.txt (12.8 KB) 7260_lspci.txt (12.2 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #552] (New) X201 not booting with edk2 payload
by Maya Matuszczyk 01 Sep '24

01 Sep '24

Issue #552 has been reported by Maya Matuszczyk. ---------------------------------------- Bug #552: X201 not booting with edk2 payload https://ticket.coreboot.org/issues/552 * Author: Maya Matuszczyk * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2024-08-18 * Affected hardware: x201 ---------------------------------------- Hello, I tried to update my x201 with a new version of coreboot(I lost the working one). After building(using default config + set to x201 + bigger cbfs + linear high-res framebuffer) with latest release I couldn't get anything with edk2 to boot on it. I've tried changing `RESOURCE_ALLOCATION_TOP_DOWN` and using newer/older tags of MrChromebox's edk2 fork. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 30 Aug '24

30 Aug '24

Dear community, Please note that we have an upcoming coreboot leadership meeting scheduled for Wednesday, September 4, 2024.[1] Kindly take a moment to update the current agenda with matters you wish to see discussed during the meeting.[2] Thank you. Best regards, Mina Asante. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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[coreboot - Bug #553] (New) M95M02 write failure
by Miklos Marton 30 Aug '24

30 Aug '24

Issue #553 has been reported by Miklos Marton. ---------------------------------------- Bug #553: M95M02 write failure https://ticket.coreboot.org/issues/553 * Author: Miklos Marton * Status: New * Priority: Normal * Target version: none * Start date: 2024-08-21 * Affected hardware: STLinkV3 * Affected OS: Linux ---------------------------------------- While trying to add support for EEPROM devices (which lacks the erase capability) I came across some issues with implementing it. The only device so far which lacks erase capability is the M95M02. When trying to write it via force I receieve a SIGSEV and the following output: ``` shell 08:17:18: Debugging /home/mm/Projektek/flashrom/flashrom -p stlinkv3_spi -c M95M02 -f -w /tmp/myfile ... could not find '.gnu_debugaltlink' file for /lib/x86_64-linux-gnu/libcap.so.2 flashrom 1.4.0-rc2 (git:v1.4.0-rc2-1-gbd3c5f31) on Linux 6.8.0-40-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Connected to STLink V3 with bridge FW version: 5 SCK frequency set to 750 kHz Assuming ST flash chip "M95M02" (256 kB, SPI) on stlinkv3_spi. === This flash part has status UNTESTED for operations: WP The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. You can also try to follow the instructions here: https://www.flashrom.org/contrib_howtos/how_to_mark_chip_tested.html Thanks for your help! spi_get_opcode_from_erasefn: unknown erase function (0x1). Please report this at flashrom(a)flashrom.org ``` Backtrace: ``` >~"#0 0x000055555558f047 in check_block_eraser (flash=flash@entry=0x7fffffffd9d0, k=k@entry=0, log=log@entry=0) at flashrom.c:489\n" >~"#1 0x000055555558f0c7 in count_usable_erasers (flash=flash@entry=0x7fffffffd9d0) at flashrom.c:508\n" >~"#2 0x000055555558f15f in chip_safety_check (flash=flash@entry=0x7fffffffd9d0, force=1, read_it=read_it@entry=0, write_it=write_it@entry=1, erase_it=erase_it@entry=0, verify_it=verify_it@entry=1) at flashrom.c:2019\n" >~"#3 0x0000555555591426 in prepare_flash_access (flash=flash@entry=0x7fffffffd9d0, read_it=read_it@entry=false, write_it=write_it@entry=true, erase_it=erase_it@entry=false, verify_it=verify_it@entry=true) at flashrom.c:2121\n" >~"#4 0x0000555555591821 in flashrom_image_write (flashrom_flashctx=flashrom_flashctx@entry=0x7fffffffd9d0, buffer=buffer@entry=0x7ffff7ea5010, buffer_len=buffer_len@entry=262144, refbuffer=refbuffer@entry=0x0) at flashrom.c:2287\n" >~"#5 0x00005555555795d6 in do_write (flash=flash@entry=0x7fffffffd9d0, filename=0x55555565c2c0 \"/tmp/myfile\", referencefile=0x0) at cli_classic.c:535\n" >~"#6 0x000055555557a455 in main (argc=<optimized out>, argv=<optimized out>) at cli_classic.c:1255\n" ``` -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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2024-08-28 coreboot Group Review Session
by mina＠coreboot.org 26 Aug '24

26 Aug '24

Hello coreboot! We have an upcoming group review session on Wednesday: https://meet.google.com/kpu-yozw-gtt Check the coreboot calendar for the time in your timezone: https://coreboot.org/calendar.html As usual, we’ll begin by reviewing a few RFC patches together, then switch to review patches individually for a bit, but everyone will be available if you have questions about the patch you’re reviewing. Here’s the link to the list of patches to be reviewed: https://docs.google.com/spreadsheets/d/1io-tewVlkX3PAkhR9ttCKjJXiXR9Emy6qsY… 61#gid=1189723661 Please add any specific patches you'd like the group to review to the top of the sheet. Given the limited time for our review session, any reviews completed beforehand would be greatly appreciated. Thank you. Best regards, Mina.

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[coreboot - Other #554] (New) Do not follow ch1p's guide on flashing Thinkpad W530 with only 8MB chip!!
by Simon Dominic 23 Aug '24

23 Aug '24

Issue #554 has been reported by Simon Dominic. ---------------------------------------- Other #554: Do not follow ch1p's guide on flashing Thinkpad W530 with only 8MB chip!! https://ticket.coreboot.org/issues/554 * Author: Simon Dominic * Status: New * Priority: Normal * Target version: none * Start date: 2024-08-23 ---------------------------------------- I had to learn this the hard way and (literally) pay the price (for it to be repaired) for following this guide (both on their own [website](https://ch1p.io/coreboot-t530-one-chip/) and a [reddit post](https://www.reddit.com/r/coreboot/comments/956ymu/howto_flash_coreboo…). I often make tweaks to my coreboot config which often breaks my system by not being able to boot, and thus requires a fully disassembly to access the 4MB chip to externally flash. As you can imagine, doing this every time I mess up is annoying, and so the idea that I could do it with just the 8MB chip, which is easily accessible, was very attractive. Right off the bat, I'll say this this method causes so many problems and going through the pain and frustration is not worth the convenience of not doing full disassembly. I was in contact with ch1p who was very helpful in trying to help me out. However, it must be said that this guide should **NOT** be followed! This completely messes up the bios chips' firmware tabling, making it impossible to internally or externally flash (while the chips were still on the motherboard). You cannot read or write from either of the chips, and the 8MB chip thinks it 4MB. I would get errors like this: ``` Reading old flash chip contents... done. Erasing and writing flash chip... FAILED at 0x00000000! Expected=0xff, Found=0x16, failed byte count from 0x00000000-0x00000fff: 0x1000 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000000! Expected=0xff, Found=0x16, failed byte count from 0x00000000-0x0000ffff: 0x10000 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000000! Expected=0xff, Found=0x16, failed byte count from 0x00000000-0x0000ffff: 0x10000 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000000! Expected=0xff, Found=0x16, failed byte count from 0x00000000-0x003fffff: 0x400000 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000000! Expected=0xff, Found=0x16, failed byte count from 0x00000000-0x003fffff: 0x400000 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Looking for another erase function. Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Apparently at least some data has changed. Your flash chip is in an unknown state. Please report this to the mailing list at flashrom(a)flashrom.org or on IRC (see https://www.flashrom.org/Contact for details), thanks! ``` Thanks to [this](https://github.com/flashrom/flashrom/issues/190) github issue, I figured the only way to fix this was to have the chips physically removed and then flash them. Since I can't solder, I paid someone to do it (they charge for disassembly, so saved by dissembling myself and giving them just the motherboard). The bad news is the 8MB always thinks it's 4MB, so impossible to externally flash that chip. The good news is the 4MB chip is perfectly fine, which is great because that's the chip for the actually bios. From there, you can internally flash (both chips), so that problem sorts itself out. I had to pay someone to fix the mess that the guide caused. If someone with a Thinkpad W530 happens to stumble upon this post, you will save yourself time, pain and money by ignoring the guide and just dealing with full disassembly. It's not worth it. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #549] (New) coreboot 24.05: SeaBIOS Windows 10/11 BSOD "ACPI BIOS ERROR" (Thinkpad W530)
by Simon Dominic 23 Aug '24

23 Aug '24

Issue #549 has been reported by Simon Dominic. ---------------------------------------- Bug #549: coreboot 24.05: SeaBIOS Windows 10/11 BSOD "ACPI BIOS ERROR" (Thinkpad W530) https://ticket.coreboot.org/issues/549 * Author: Simon Dominic * Status: New * Priority: Normal * Category: board support * Target version: master * Start date: 2024-07-31 * Affected versions: master * Affected hardware: Lenovo ThinkPad W530 * Affected OS: Windows 10/11 ---------------------------------------- When using the latest coreboot (i.e. using command `git clone https://review.coreboot.org/coreboot`), which is currently 24.05, to build a rom for Thinkpad W530, I get BSOD with "ACPI BIOS ERROR" when trying to boot into Windows 10 or 11 from SeaBIOS. Even just booting from a Windows install usb will show this error. This is even with incorporating the vga bios files (so i can external displays to work) - see my defconfig. Did consider using EDK2 apparently Windows support is pretty solid, but could never make a successful build - not that `make` command had errors, but once flashing, would just having white underscore and have to recover with external flashing. A separate issue to write about in and of itself, but I prefer SeaBIOS so I'll be sticking with that. I am quite new to coreboot - using for only about 2-3 months now. Let me know if there is further information I should provide. ---Files-------------------------------- defconfig (590 Bytes) w530_bsod.jpg (1.98 MB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #536] (New) Cannot build coreboot-sdk
by Michał Żygowski 22 Aug '24

22 Aug '24

Issue #536 has been reported by Michał Żygowski. ---------------------------------------- Bug #536: Cannot build coreboot-sdk https://ticket.coreboot.org/issues/536 * Author: Michał Żygowski * Status: New * Priority: Normal * Assignee: Martin Roth * Target version: none * Start date: 2024-04-24 ---------------------------------------- I have just tried building coreboot-sdk from scratch and could not get past the step of installing the required packages. Found out that diffutils dependency on libcurl4t64 break libcurl4 (change apt-get to apt to see verbose information message like below): ``` shell > [coreboot-sdk 2/4] RUN useradd -p locked -m coreboot && apt-get -qq update && apt -qqy install --no-install-recommends bash-completion bc bison bsdextrautils bzip2 ca-certificates ccache cmake cscope curl device-tree-compiler dh-autoreconf diffutils exuberant-ctags flex g++ gawk gcc git gnat-13 golang graphicsmagick-imagemagick-compat graphviz lcov less libcapture-tiny-perl libcrypto++-dev libcurl4 libcurl4-openssl-dev libdatetime-perl libelf-dev libfreetype-dev libftdi1-dev libglib2.0-dev libgmp-dev libgpiod-dev libjaylink-dev liblzma-dev libnss3-dev libncurses-dev libpci-dev libreadline-dev libssl-dev libtimedate-perl libusb-1.0-0-dev libxml2-dev libyaml-dev m4 make meson msitools neovim ninja-build openssh-client openssl parted patch pbzip2 pkg-config python3 python-is-python3 qemu-system-arm qemu-system-misc qemu-system-ppc qemu-system-x86 rsync sharutils shellcheck unifont unzip uuid-dev vim-common wget xz-utils zlib1g-dev && apt-get clean: 2.106 2.106 WARNING: apt does not have a stable CLI interface. Use with caution in scripts. 2.106 2.841 diffutils is already the newest version (1:3.10-1). 2.841 diffutils set to manually installed. 2.841 Some packages could not be installed. This may mean that you have 2.841 requested an impossible situation or if you are using the unstable 2.841 distribution that some required packages have not yet been created 2.841 or been moved out of Incoming. 2.841 The following information may help to resolve the situation: 2.841 2.841 Unsatisfied dependencies: 3.001 libcurl4t64 : Breaks: libcurl4 (< 8.7.1-3) 3.004 Error: Unable to correct problems, you have held broken packages. ``` Changing libcurl4 to libcurl4t64 allows the docker to continue the build process of coreboot-sdk. But is this the right thing to do? -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot August 2024