coreboot March 2024

coreboot@coreboot.org

19 participants
34 discussions

GRUB2_SECONDARY_PAYLOAD: max possible module set + unavailable modules
by Mike Banon 10 Mar '24

10 Mar '24

Good day! I am trying to ensure the best feature set for a GRUB2 secondary payload of SeaBIOS. First of all, I checked what GRUB2 modules I have in a fully-updated Artix (arch without systemd) installation: ls -al /boot/grub/i386-pc/ | cut -c44- | awk '{ print substr( $0, 1, length($0)-4 ) }' | tr '\n' ' ' Then I tried using this list as a value for CONFIG_GRUB2_EXTRA_MODULES (could not set it with 'make menuconfig' because it was way too long, so had to edit a ./coreboot/.config manually) - but for some reason not all GRUB2 modules are available: while trying to build, I constantly got the errors like: ... config.status: creating grub ./grub-mkstandalone: error: cannot open `grub-core//pxechain.mod': No such file or directory. make[2]: *** [Makefile:15040: default_payload.elf] Error 1 make[1]: *** [Makefile:45: grub2] Error 2 make: *** [payloads/external/Makefile.mk:276: grub2] Error 2 - and had to remove the "missing modules" from this variable one-by-one. Eventually I got the max possible GRUB2 module set - please see attachments (without any modules at all, img/grub2 occupies 472 KB at CBFS; with all these modules - 710 KB). However, what worries me is why these modules are unavailable at coreboot+SeaBIOS version of GRUB2 : biosdisk bufio cacheinfo cbtable command core drivemap font freedos fs gfxterm legacycfg legacy_password_test load lsapm moddep modinf ntldr partmap plan9 pxechain pxe sendkey truecrypt vbe vga vga_text video_fb video Some of those missing ones could be valuable - like a truecrypt module... Do you know why they are missing and how to debug this? -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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looking for someone to help on coreboot port to visionfive2 board
by ron minnich 07 Mar '24

07 Mar '24

during a recent RISE meeting, I conveyed the good news that Max and 9elements had released the SiFive unmatched port and it was upstreamed! That was great. People seemed interested. Next request: Starfive visionfive2. Now, we do have an oreboot port, so there is a code base to reference. If somebody would like to look at getting this board ported, it would be a big help.

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2024-03-06 - coreboot Leadership Meeting minutes
by mina＠coreboot.org 07 Mar '24

07 Mar '24

# 2024-03-06 - coreboot Leadership Meeting minutes ## Announcement: OSFF ByteTalks - [https://osfw.foundation/events/bytetalks-vol.-1/]. OSFC will be in Bochum Germany - September 3-5 - [https://www.osfc.io/]. ## Attendees: Martin Roth, Mina Asante, Julius Werner, Daniel Maslowski, Jonathan Hall, Matt Devillier, Nicholas Chin, Nico Huber, Jay Talbott, Felix Singer, Werner Zeh, Marshall Dawson, Felix Held, David Hendricks, Jules Irenge, Max Brune. ## Open Action Items * 2024-03-06 * [Open] Martin: To update documentation on gerrit contributing guidelines. * https://doc.coreboot.org/contributing/index.html * 2024-01-10 * [Open] Werner: Push patch based on https://ticket.coreboot.org/issues/522 * Nico: https://review.coreboot.org/q/topic:enforce_region_api * Open Daniel: Look at how we want to localize (non console) strings for coreboot. Long term project. ## Minutes ### [Martin] -1 should be a privilege for coreboot reviewers along with +2 rights. * Since 2016, all registered users have had -1 rights. Back then, we didn’t block on unresolved comments, so giving a -1 was the only good way to get attention for an issue. This is no longer the case, and I feel that we should go back to having -1 rights be one of the privileges given to contributors. * There’s no incident - We just don’t need to give -1 to every registered user anymore. This has been superseded by making people address all open patches. * Current status: * Registered users: -1 to +1 * Developers: -1 to +2 * Core developers: -2 to +2 * Proposed: * Registered users: 0 to +1 * Developers: -1 to +2 * Core developers: -2 to +2 * FelixS: If people can give +1, they should be allowed to give -1. * Martin: So should we give -2 privileges to everyone with +2 privileges as well? * FelixS: The -1 allows me to see attitudes about things without needing to read come * Martin: I feel like the -1 rights should go to people who have actually submitted patches - it’s not hard. * Max, David, Daniel: Agreed * FelixS: Disagree * Documentation needs to be updated. * We can change it back if there are issues. ### [Martin] Implementing fuzzing testing at coreboot. * First test at [https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/util…] * Any APIs & anything loaded out of SPI should be fuzzed when possible. * Add to ongoing projects. ### [Martin] Gtiles is currently down * FelixS added some firewallish rules to the web server to block some bots. Still not very efficient - each Bot needs to be blocked individually. * We don’t get IP addresses of requests. * Daniel: Search engines also index GitHub on which we have mirrored out repos, so when it’s about code visibility/discoverability, we can block crawlers completely to lower the impact on our own infra. People can use the GitHub viewer and Gitiles alike, giving just a different view on the same data. ### [FelixS] Revisit register naming for I2c device registers: * See (https://review.coreboot.org/c/coreboot/+/77098) - This only changes the *coreboot* structures, not device #defines and device specific structures. * After discussion about this patch, there’s more support for keeping internal naming consistent, even if it doesn’t match the names from the specs. * Werner: Keep the names consistent with the datasheets even if they don’t match the coreboot structures. Max: Agreed * Martin & FelixS would prefer to change. ### [Martin] Renaming SPI master/slave * There’s no specific SPI spec, but there are a number of major companies who have changed the names in their specifications. Most notably, Intel has changed the names in the eSPI specification to controller/target. \ Unfortunately, there’s no real agreement on what to change the names to: \ [https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Alternative_termi…] * Martin’s proposal would be to go with the eSPI names of controller/target as eSPI. \ * Matt and Werner agree. * Julius points out "main" and "sub" preserves MISO/MOSI and is currently used on Wikipedia. * Max likes this. David +1 * Nico: This seems a bit forced * SPI: main/sub and eSPI: controller/target (Devices use whatever their datasheet says) * FelixS: Let’s look at what the linux kernel does. ### [Martin] Designing a coreboot Poster & Brochure for conferences * We’d like to design a poster & brochure to have at conferences and other places where coreboot information is desired. * [https://docs.google.com/document/d/1l-dSWram1vpq6-fYYqecYmOXCpj_7YXSnBx-kaK…] * Please comment or contribute * Marvin has a flyer * Add a payload section - Most used payloads - add logos * Adding a bunch of qr codes pointing to the website for the vendors & consultants * Shortened links as well or instead * Make part of the domain instead - gsoc.coreboot.org instead of https://doc.coreboot.org/contributing/gsoc.html ### [Martin] Info only: The 24.02 release is complete and announced. * Next release will be Mid-May. ### [FelixS] Not applying to GSOC this year - deadline is passed. * Not many people interested in mentoring - This is a big time investment. # Next meeting * March 20, 2024. * [Meeting link](https://bbb.sfconservancy.org/b/mar-sfn-e22-axi). * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice * Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes [2024-03-06](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1… 1).

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 06 Mar '24

06 Mar '24

Dear community, Please note that the upcoming coreboot leadership meeting is scheduled for next Wednesday, March 6, 2024.[1] You are welcome to update the current agenda items with matters you wish to see addressed during the meeting.[2] ## Current Agenda Items ### [Martin] -1 should be a privilege for coreboot reviewers along with +2 rights. * Since 2016, all registered users have had -1 rights. Back then, we didn’t block on unresolved comments, so giving a -1 was the only good way to get attention for an issue. This is no longer the case, and I feel that we should go back to having -1 rights be one of the privileges given to contributors. ### [Martin] Implementing fuzzing testing at coreboot. * First test at https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/util… ### [FelixS] Revisit register naming for I2c device registers: * See https://review.coreboot.org/c/coreboot/+/77098 * After discussion about this patch, there’s more support for keeping internal naming consistent, even if it doesn’t match the names from the specs. ### [Martin] Renaming SPI master/slave * There’s no specific SPI spec, but there are a number of major companies who have changed the names in their specifications. Most notably, Intel has changed the names in the eSPI specification to controller/target. Unfortunately, there’s no real agreement on what to change the names to: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Alternative_termi… ### [Martin] Designing a coreboot Poster & Brochure for conferences * We’d like to design a poster & brochure to have at conferences and other places where coreboot information is desired. ### [Martin] Info only: The 24.02 release is complete and announced. [1](https://coreboot.org/calendar.html). [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK….

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EM100Pro-G3 sporadically stops working
by Corvin Köhne 06 Mar '24

06 Mar '24

Hi, I'm currently having some issues using the new EM100Pro-G3 and would like to know if someone has seen such issues before and may have a solution. The EM100Pro-G3 sporadically stops working properly. I can reproduce the issue within a few minutes by running the following steps in a loop: 1. power off the board 2. em100 \ --device EMxxxxxx \ --stop \ --set <chip> \ --download <rom> \ --verify \ --start 3. power on the board * the board is configured to netboot a linux 4. wait until linux is reachable by ssh 5. goto 1 After some iterations, the board isn't able to boot any more. Even if I power cycle the board, it doesn't boot. It doesn't even reach it's first POST. Reloading the ROM into the EM100 (repeating step 2), solves the issue. I'm currently trying to gather more information about the issue. What I do know right now: 1. Reloading the ROM without physically touching anything solves the issue. 2. It doesn't matter if I connect the USB connector + power adapter or only the USB connector to the EM100Pro-G3. 3. I've recently exchanged the EM100Pro-G3 with the older EM100Pro-G2. The board is running fine for several hours right now without any issues. 4. If the board is unable to boot, `em100 --device EMxxxxxx --trace` does return some data. I don't think it's a physical issue, e.g. signal integrity issue, as I'm not touching the whole system (see 1 + 2). I also don't think that it's a sporadic issue of my ROM file as it's working with the old G2 (see 3). Maybe the ROM isn't loaded correctly into the EM100 which causes it to return wrong data (see 1 + 4)? As said, the board is currently connected to a G2. I'm going to keep this test running for a while. If I can't reproduce the issue on the G2, I'm going to switch back to the G3 and try to gather some more information. What I'm going to check next is if the ROM returned by `em100 --device EMxxxxxx --upload <rom>` matches the desired ROM. Any help how to debug or solve this issue is highly appreciated! -- Many thanks in advance, Corvin

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Re: Are we running libpayload unit tests in the CI?
by Martin Roth 04 Mar '24

04 Mar '24

Hi Julius, I've fixed the issue you were seeing. Thanks for bringing it to our attention. There were 2 things that were contributing to jenkins not seeing the libpayload files: 1) They were deeper in the tree than we were looking for junit*.xml files. These were only getting picked up two levels deep into the payloads directory: payloads/*/*/junit*.xml 2) We were also looking for junit.xml files anywhere in the tree, but the output files only match junit*.xml files. Here's the list of files we needed to find: ./payloads/libpayload/build/coverage/junit-libpayload-tests-build.xml ./payloads/libpayload/build/coverage/junit-libpayload-tests_libcbfs_cbfs-no-verification-has-sha512-test(tests).xml ./payloads/libpayload/build/coverage/junit-libpayload-tests_libcbfs_cbfs-no-verification-no-sha512-test(tests).xml ./payloads/libpayload/build/coverage/junit-libpayload-tests_libcbfs_cbfs-verification-has-sha512-test(tests).xml ./payloads/libpayload/build/coverage/junit-libpayload-tests_libcbfs_cbfs-verification-no-sha512-test(tests).xml ./payloads/libpayload/build/coverage/junit-libpayload-tests_libcbfs_cbfs-lookup-has-fallback-test(tests).xml ./payloads/libpayload/build/coverage/junit-libpayload-tests_libcbfs_cbfs-lookup-no-fallback-test(tests).xml ./payloads/libpayload/build/coverage/junit-libpayload-tests_libc_fmap_locate_area-test(tests).xml ./payloads/libpayload/build/coverage/junit-libpayload-tests_drivers_speaker-test(tests).xml I've updated the general pattern to find junit*.xml files anywhere in the tree, and now they're seen by the jenkins log collector. In the output of https://qa.coreboot.org/job/coreboot-gerrit/253059/ you can see that we now get 4 errors: Test Result (4 failures / +4) tests_libcbfs_cbfs-lookup-has-fallback-test(tests).test_cbfs_unverified_area_map, RW, aligned tests_libcbfs_cbfs-lookup-has-fallback-test(tests).test_cbfs_unverified_area_map, RW, unaligned tests_libcbfs_cbfs-lookup-no-fallback-test(tests).test_cbfs_unverified_area_map, RW, aligned tests_libcbfs_cbfs-lookup-no-fallback-test(tests).test_cbfs_unverified_area_map, RW, unaligned Thanks again for helping to fix this problem. Martin Feb 28, 2024, 16:22 by jwerner(a)chromium.org: > Hmm... well, I just uploaded a CL that clearly breaks one of the > tests, and Jenkins still gave me a Verified+1: > https://review.coreboot.org/80788 > > I also don't see any info about the tests running on the test report > (https://qa.coreboot.org/job/coreboot-gerrit/252941/testReport/(root)/). > So if the tests are running (and the code you pointed out strongly > looks like they should be), it's probably a problem with reading back > the test results? How does Jenkins collect those XML files? > > On Tue, Feb 27, 2024 at 7:04 PM Martin Roth <gaumless(a)tutanota.com> wrote: > >> >> Hey Julius, >> Here's what we running: >> https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/util… >> >> Martin >> Feb 27, 2024 at 18:31 by jwerner(a)chromium.org: >> >> > Hi, >> > >> > We've had unit test support in libpayload for over two years now, but >> > I just noticed that it doesn't look like we're actually running them >> > in the CI? E.g. if I look through a test run like this >> > https://qa.coreboot.org/job/coreboot-gerrit/252761/testReport/(root)/ >> > I can't find them anywhere (most of them have confusingly similar >> > names with coreboot unit tests, but "fmap_locate_area-test" is a >> > unique one). >> > >> > Is that intended or an oversight? Would it be easy to fix? (I'm not >> > super familiar with how the tests are integrated into Jenkins, but the >> > libpayload framework is pretty much a direct copy of the coreboot >> > framework, so if we can run the coreboot ones hopefully it should be >> > easy to run the libpayload ones as well?) >> > _______________________________________________ >> > coreboot mailing list -- coreboot(a)coreboot.org >> > To unsubscribe send an email to coreboot-leave(a)coreboot.org >> > >> > _______________________________________________ > coreboot mailing list -- coreboot(a)coreboot.org > To unsubscribe send an email to coreboot-leave(a)coreboot.org >

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I missed the 24.02 boat on a patch.
by Keith Hui 04 Mar '24

04 Mar '24

Hi all, I missed the memo about the 24.02 release where I should have asked for this patch to be reviewed: mb/asus/p8x7x-series: Revert to native max_mem_clock_mhz of 800 https://review.coreboot.org/c/coreboot/+/79726 I'm trying to get a setting back to where it was where it turns out it didn't really break my board. I just put a tag there trying to make sure it gets into 24.05, but can it get a review whether it's worth a point release? Thanks and sorry for the trouble. Keith

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[coreboot - Bug #530] (New) fatal: unable to access 'https://git.seabios.org/seabios.git/': The requested URL returned error: 502
by Paul Menzel 03 Mar '24

03 Mar '24

Issue #530 has been reported by Paul Menzel. ---------------------------------------- Bug #530: fatal: unable to access 'https://git.seabios.org/seabios.git/': The requested URL returned error: 502 https://ticket.coreboot.org/issues/530 * Author: Paul Menzel * Status: New * Priority: Normal * Category: infrastructure * Target version: none * Start date: 2024-03-04 ---------------------------------------- I am unable to access the SeaBIOS archive: $ LANG= git fetch fatal: unable to access 'https://git.seabios.org/seabios.git/': The requested URL returned error: 502 -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot versions 24.02 and 24.02.01 have been released
by coreboot org 03 Mar '24

03 Mar '24

The announcement on the blog is here: https://blogs.coreboot.org/blog/2024/03/01/coreboot-24-02-and-24-02-1-relea… coreboot 24.02 release ======================================================================== The coreboot project is happy to announce our release for February 2024. Over the past three months, our contributors have focused on refining the coreboot codebase, generally prioritizing cleanup and quality enhancements. We extend our gratitude to all the contributors who have dedicated their time and expertise. Thank you for your invaluable contributions to this vital phase of maintenance and optimization. The next release is scheduled for mid-May. ### Release number format update The previous release was the last to use the incrementing 4.xx release name scheme. For this and future releases, coreboot has switched to a Year.Month.Sub-version naming scheme. As such, the next release, scheduled for May of 2024 will be numbered 24.05, with the sub-version of 00 implied. If we need to do a fix or incremental release, we'll append the values .01, .02 and so on to the initial release value. ### The master branch is being deleted The coreboot project changed from master to main roughly 6 months ago, and has been keeping the two branches in sync since then to ease the transition. As of this release, we are getting rid of the master branch completely. Please make sure any scripts you're using that reference the 'master' branch have been switched to 'main'. Release 24.02.1 --------------- ### lib/rtc: Fix off-by-one error in February day count in leap year The month argument passed to rtc\_month\_days is 0-based, not 1-based. This results in the RTC being reverted to the build date constantly on 29th February 2024. Significant or interesting changes ---------------------------------- ### acpi: Add Arm IO Remapping Table structures Input Output Remapping Table (IORT) represents the IO topology of an Arm based system. Document number: ARM DEN 0049E.e, Sep 2022 ### acpi: Add PPTT support This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board. ### acpi: Add support for WDAT table This commit lays the groundwork for implementing the ACPI WDAT (Watchdog Action Table) table specification. The WDAT is a special ACPI table introduced by Microsoft that describes the watchdog for the OS. Platforms that need to implement the WDAT table must describe the hardware watchdog management operations as described in the specification. See â€œLinks to ACPI-Related Documentsâ€ (http://uefi.org/acpi) under the heading â€œWatchdog Action Tableâ€ . ### lib/jpeg: Replace decoder with Wuffs' implementation To quote its repo[0]: Wuffs is a memory-safe programming language (and a standard library written in that language) for Wrangling Untrusted File Formats Safely. Wrangling includes parsing, decoding and encoding. It compiles its library, written in its own language, to a C/C++ source file that can then be used independently without needing support for the language. That library is now imported to src/vendorcode/wuffs/. This change modifies our linters to ignore that directory because it's supposed to contain the wuffs compiler's result verbatim. Nigel Tao provided an initial wrapper around wuffs' jpeg decoder that implements our JPEG API. I further changed it a bit regarding data placement, dropped stuff from our API that wasn't ever used, or isn't used anymore, and generally made it fit coreboot a bit better. Features are Nigel's, bugs are mine. This commit also adapts our jpeg fuzz test to work with the modified API. After limiting it to deal only with approximately screen sized inputs, it fuzzed for 25 hours CPU time without a single hang or crash. This is a notable improvement over running the test with our old decoder which crashes within a minute. Finally, I tried the new parser with a pretty-much-random JPEG file I got from the internet, and it just showed it (once the resolution matched), which is also a notable improvement over the old decoder which is very particular about the subset of JPEG it supports. In terms of code size, a QEmu build's ramstage increases from 128060 bytes decompressed (64121 bytes after LZMA) to 172304 bytes decompressed (82734 bytes after LZMA). [0] https://github.com/google/wuffs Additional coreboot changes --------------------------- * Rename Makefiles from .inc to .mk to better identify them * SPI: Add GD25LQ255E and IS25WP256D chip support * device: Add support for multiple PCI segment groups * device: Drop unused multiple downstream link support * device: Rename bus and link_list to upstream and downstream * Updated devicetree files for modern Intel platforms to use chipset.cb * Updated xeon-sp to use the coreboot allocator Changes to external resources ----------------------------- ### Toolchain updates * Add buildgcc support for Apple M1/M2 devices * Upgrade GCC from 11.4.0 to 13.2.0 * Update CMake from 3.26.4 to 3.27.7 * Uprev to Kconfig from Linux 6.7 ### Git submodule pointers * /3rdparty/amd_blobs: Update from commit id e4519efca7 to 64cdd7c8ef (5 commits) * /3rdparty/arm-trusted-firmware: Update from commit id 88b2d81345 to 17bef2248d (701 commits) * /3rdparty/fsp: Update from commit id 481ea7cf0b to 507ef01cce (16 commits) * /3rdparty/intel-microcode: Update from commit id 6788bb07eb to ece0d294a2 (1 commit) * /3rdparty/vboot: Update from commit id 24cb127a5e to 3d37d2aafe (121 commits) ### External payloads * payload/grub2: Update from 2.06 to 2.12 * payload/seabios: Update from 1.16.2 to 1.16.3 Platform Updates ---------------- ### Added mainboards: * Google: Dita * Google: Xol * Lenovo: ThinkPad X230 eDP Mod (2K/FHD) ### Removed Mainboards * Google -> Primus4ES Statistics from the 4.22 to the 24.02 release -------------------------------------------- * Total Commits: 815 * Average Commits per day: 8.63 * Total lines added: 105433 * Average lines added per commit: 129.37 * Number of patches adding more than 100 lines: 47 * Average lines added per small commit: 41.34 * Total lines removed: 16534 * Average lines removed per commit: 20.29 * Total difference between added and removed: 88899 * Total authors: 111 * New authors: 19 Significant Known and Open Issues --------------------------------- * AMD chromebooks will not work with the signed PSP_verstage images and the version of verstage used in coreboot 24.02. ## Issues from the coreboot bugtracker: https://ticket.coreboot.org/ ### coreboot-wide or architecture-wide issues ```eval_rst +-----+-----------------------------------------------------------------+ | # | Subject | +=====+=================================================================+ | 522 | 'region_overlap()' issues due to an integer overflow. | +-----+-----------------------------------------------------------------+ | 519 | make gconfig - could not find glade file | +-----+-----------------------------------------------------------------+ | 518 | make xconfig - g++: fatal error: no input files | +-----+-----------------------------------------------------------------+ ``` ### Payload-specific issues ```eval_rst +-----+-----------------------------------------------------------------+ | # | Subject | +=====+=================================================================+ | 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled | +-----+-----------------------------------------------------------------+ | 496 | Missing malloc check in libpayload | +-----+-----------------------------------------------------------------+ | 484 | No USB keyboard support with secondary payloads | +-----+-----------------------------------------------------------------+ | 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT | +-----+-----------------------------------------------------------------+ ``` ### Platform-specific issues ```eval_rst +-----+-----------------------------------------------------------------+ | # | Subject | +=====+=================================================================+ | 517 | lenovo x230 boot stuck with connected external monitor | +-----+-----------------------------------------------------------------+ | 509 | SD Card hotplug not working on Apollo Lake | +-----+-----------------------------------------------------------------+ | 507 | Windows GPU driver fails on Google guybrush & skyrim boards | +-----+-----------------------------------------------------------------+ | 506 | APL/GML don't boot OS when CPU microcode included "from tree" | +-----+-----------------------------------------------------------------+ | 505 | Harcuvar CRB - 15 of 16 cores present in the operating system | +-----+-----------------------------------------------------------------+ | 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled | +-----+-----------------------------------------------------------------+ | 495 | Stoney Chromebooks not booting PSPSecureOS | +-----+-----------------------------------------------------------------+ | 478 | X200 booting Linux takes a long time with TSC | +-----+-----------------------------------------------------------------+ | 474 | X200s crashes after graphic init with 8GB RAM | +-----+-----------------------------------------------------------------+ | 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb | +-----+-----------------------------------------------------------------+ | 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit | +-----+-----------------------------------------------------------------+ | 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking | +-----+-----------------------------------------------------------------+ | 448 | Thinkpad T440P ACPI Battery Value Issues | +-----+-----------------------------------------------------------------+ | 446 | Optiplex 9010 No Post | +-----+-----------------------------------------------------------------+ | 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) | +-----+-----------------------------------------------------------------+ | 427 | x200: Two battery charging issues | +-----+-----------------------------------------------------------------+ | 412 | x230 reboots on suspend | +-----+-----------------------------------------------------------------+ | 393 | T500 restarts rather than waking up from suspend | +-----+-----------------------------------------------------------------+ | 350 | I225 PCIe device not detected on Harcuvar | +-----+-----------------------------------------------------------------+ ``` coreboot Links and Contact Information -------------------------------------- * Main Web site: https://www.coreboot.org * Downloads: https://coreboot.org/downloads.html * Source control: https://review.coreboot.org * Documentation: https://doc.coreboot.org * Issue tracker: https://ticket.coreboot.org/projects/coreboot * Donations: https://coreboot.org/donate.html

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[coreboot - Bug #121] T520: Hangs in OS
by Anastasios Koutian 03 Mar '24

03 Mar '24

Issue #121 has been updated by Anastasios Koutian. Martin Zwicknagl wrote in #note-46: > Hello, > > I can report, that I had NO freezes for a month now. > > During a RAM upgrade to 16GB I have replaced one 2GB Samsung SODIMM (2GB 1Rx8 PC3-10600s-09-10-ZZZ, M471B5773CHS-CH9 1149) > with a SODIMM [Crucial CT102464BF160B 8GB Speicher (DDR3L, 1600 MT/s, PC3L-12800, SODIMM, 204-Pin)]. > The laptop is now using two identical Crucial SODIMMs. > > The problem is gone. I do not need any ``intel_idle.max_cstate`` tricks anymore. My T520 is using all cores, hyperthreading, all cstates (and turbo boost). > > I think ticket 178 is also solved. Who can close 178? > > Cheeers > Martin Hello all, I installed the exact same SODIMMs (Crucial CT102464BF160B) as the message quoted above and achieved four days continuous uptime with no issues. I eventually had to reboot due to a necessary update, so it might be a premature conclusion. I will keep the system running for as long as I can to confirm. I haven't gotten around to comparing with MSRs on stock firmware yet, but will once I have spare time. ---------------------------------------- Bug #121: T520: Hangs in OS https://ticket.coreboot.org/issues/121#change-1771 * Author: Firstname Lastname * Status: In Progress * Priority: Normal * Category: chipset configuration * Start date: 2017-06-09 * Affected hardware: SNB, IVY * Affected OS: - ---------------------------------------- I have been running coreboot since 2017.04.15 and have experienced hangs ever since then. It was suggested by folk on the IRC that I run memtest to check for incorrect raminit causing errors, however I have run memtest for 12 hours straight with no errors. Due to the ambiguous nature of the hangs (immediate freeze with no warning signs, audio gets stuck repeating the last 50ms or so of noise, not sure what this effect is called) I don't have much useful information other than the .config and dmesg. However one thing I can say with high confidence is that the hangs occur significantly more frequently in Linux (*buntu distros) than Windows 10. Within an hour of launching Linux a hang is likely, whereas Windows typically runs for many hours before a hang occurs. I considered this an insignificant anecdotal anomaly at first but over the course of the nearly 2 months I have been running coreboot it seems to be a solid trend. The hangs occur anywhere, typically during mere desktop usage or basic web browsing. Additionally there is another form of hang I experience where the screen goes black except for some sort of graphical corruption down the left side (http://i.imgur.com/4zWrlpX.jpg), whether this is related to the more common total freeze hangs I don't know but I figured I should include it nonetheless. These hangs only occur about 1:20 compared to the regular hangs. ---Files-------------------------------- config (20.7 KB) dmesg.txt (57.3 KB) cbmem-raminit.txt (62 KB) lspci.txt (29.6 KB) cpuinfo.txt (3.94 KB) defconfig (1023 Bytes) defconfig (699 Bytes) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot March 2024