coreboot March 2023

coreboot@coreboot.org

40 participants
40 discussions

440BX meminit changes testing
by Branden Waldner 01 Apr '23

01 Apr '23

Hi Keith So far I've only tested the complete patch train (73888) like previously mentioned and didn't have my serial console set up at the time. I dug out the cable from behind my desk and got it run to my work bench again, so that should help out. I'm assuming you would want logs with raminit debug enabled though and I didn't have that set last time. You had mentioned you wanted me to test 74036 specifically? I checked out the ram I was using with decode-dimms, but didn't check any other ram yet. It looks like they are both rated for CL3 @100mhz and the 133mhz stick seems to run at it's timings for 133 instead of 100? I'm running a 100mhz fsb coppermine cpu and the memory is supposed to run at the fsb speed right? It doesn't seem to use (or at least display it is using) the 100mhz timing on the oem bios either - though I haven't done enough testing to be confident of what's going on. I have some high density 256mb memory that runs at 128mb with this chipset, so I could check what the timings are on that yet. I really should have just tried to find a lot of 512mb high density to just fill out whatever sdram usage I could have. Branden

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[coreboot - Feature #477] (New) Excessive Power Draw with USB-PD
by Stan Janssen 31 Mar '23

31 Mar '23

Issue #477 has been reported by Stan Janssen. ---------------------------------------- Feature #477: Excessive Power Draw with USB-PD https://ticket.coreboot.org/issues/477 * Author: Stan Janssen * Status: New * Priority: Normal * Target version: none * Start date: 2023-03-31 * Affected hardware: Starbook MK V ---------------------------------------- I have a StarBook MK V with Coreboot connected to a Dell S2719DC external monitor that supplies 45 W of power over USB-C. However, the laptop draws more than the available 45W of power and the display shuts down with a warning message: "Excessive Power Draw from connected device". I understand that this power management feature could be handled in Coreboot. Is this a feature that could be supported in Coreboot in the future? Is there something that I could do to support the development of this feature? Is there a workaround in the meantime? Thanks! -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Provide Toolchain Binaries - The serial output of my build
by Ziqian Rong (zr1e22) 30 Mar '23

30 Mar '23

Hi, everyone I am Ziqian Rong, a 1st Electrical & Electronic Engineering student at the University of Southampton. I am interested in the "Provide Toolchain Binaries" project. I followed the tutorial and here is the serial output of my build. Hope I can get in touch with the mentor of this project. Thank you very much! Best regards, Ziqian Rong

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Coffeelake Reset S5 Problem
by cagatay bagci 29 Mar '23

29 Mar '23

Hello all,We have a custom CFL board that resembles CFL RVP-11. I compiled the code and flashed it and it started booting without problem. However after global reset, it stucks at S5 and S5 signal asserts low. Because of that, microcontroller does not power up the system. What might be the problem? Log is ending here: [INFO ] Done allocating resources.[0m[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 75 ms[0m[DEBUG] GLOBAL RESET![0m[INFO ] global_reset() called![0m[DEBUG] HECI: Global Reset(Type:1) Command Thanks,

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[coreboot - Bug #121] T520: Hangs in OS
by Anastasios Koutian 29 Mar '23

29 Mar '23

Issue #121 has been updated by Anastasios Koutian. File defconfig added Andrey A. wrote in #note-70: > T420 and IVB cpu here again. > After 9 months with intel_idle.max_cstate=4 (and last kernel and coreboot) I get a full stable system without a freeze. I have a similar setup: Mainboard: T420 CPU: i7-3940XM RAM: Corsair Vengeance 16 GB DDR3 1600 MHz (CMSX16GX3M2A1600C10) iGPU: Intel HD Graphics 4000 dGPU: NVIDIA Quadro NVS 4200M Coreboot version is CBET4000 4.16-1069-gf4905da14c using MrChromebox's old "corebootpayload" branch as payload (which is now deprecated, I think). Intel ME was stripped. Coreboot config is attached. With intel_idle.max_cstate=2 the system is stable. Any higher value results in the freezes as described above (sometimes with the glitch on the left side of the screen, sometimes without). It's weird how intel_idle.max_cstate=4 doesn't work for me. If anyone is still looking into this, I would be happy to help. ---------------------------------------- Bug #121: T520: Hangs in OS https://ticket.coreboot.org/issues/121#change-1455 * Author: Julz Buckton * Status: New * Priority: Normal * Start date: 2017-06-09 ---------------------------------------- I have been running coreboot since 2017.04.15 and have experienced hangs ever since then. It was suggested by folk on the IRC that I run memtest to check for incorrect raminit causing errors, however I have run memtest for 12 hours straight with no errors. Due to the ambiguous nature of the hangs (immediate freeze with no warning signs, audio gets stuck repeating the last 50ms or so of noise, not sure what this effect is called) I don't have much useful information other than the .config and dmesg. However one thing I can say with high confidence is that the hangs occur significantly more frequently in Linux (*buntu distros) than Windows 10. Within an hour of launching Linux a hang is likely, whereas Windows typically runs for many hours before a hang occurs. I considered this an insignificant anecdotal anomaly at first but over the course of the nearly 2 months I have been running coreboot it seems to be a solid trend. The hangs occur anywhere, typically during mere desktop usage or basic web browsing. Additionally there is another form of hang I experience where the screen goes black except for some sort of graphical corruption down the left side (http://i.imgur.com/4zWrlpX.jpg), whether this is related to the more common total freeze hangs I don't know but I figured I should include it nonetheless. These hangs only occur about 1:20 compared to the regular hangs. ---Files-------------------------------- config (20.7 KB) dmesg.txt (57.3 KB) cbmem-raminit.txt (62 KB) lspci.txt (29.6 KB) cpuinfo.txt (3.94 KB) defconfig (1023 Bytes) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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GSoC 2023 participation
by Shivani Joshi 29 Mar '23

29 Mar '23

Hello, I am Shivani Joshi, a third year computer engineering undergraduate. I am looking forward to participating in the GSOC 2023 program for coreboot. The following projects interested me while going through the list of projects. 1. Provide toolchain binaries 2. Fully support building coreboot with the Clang compiler I have already completed building coreboot on my linux system. As mentioned on the contributing page, I have begun solving the scan-build issues. I have experience with programming arm processors and have an affinity towards low-level programming. I am attaching the serial output on the terminal after building the code along with this email. Regards, Shivani

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Please Unsub me from this feed
by ivankalashnikov＠outlook.com 29 Mar '23

29 Mar '23

-- Sincerely, Ivan Kalashnikov

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GSoC 2023-Provide Toolchain Binaries
by Komal S 29 Mar '23

29 Mar '23

Hello All! This is Komal Sambhus from Mumbai, India. I had earlier expressed my interest for the project 'Provide Toolchain Binaries'. It would be great to get in touch with the mentors for this project to proceed further. Thanking You in Advance, Regards, Komal

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[GSOC 2023] Libpayload based memtest payload
by Joursoir 24 Mar '23

24 Mar '23

Hello everyone, I'm interested in participating in GSoC 2023. I would like to take part in the development of the coreboot, moreover I already have a bunch of commits in the flashrom. I find the "Libpayload based memtest payload" project interesting and have a few questions about it. 1) This project was added a few years ago, also coreboot payload of memtest based on memtest from 2019 (however, in 2022 memtest86+ v6 is released). So, maybe something has changed since that time and not reflected in the docs? I found such ticket: https://ticket.coreboot.org/issues/184 2) Do I understand correctly, that this payload should be memtest-fork with a difference that will be built on libpayload and a design that will allow multiple architectures to be added? 3) There are no mentors at the moment :( I would appreciate any feedback. -- Joursoir

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Introduction
by Yuchen He 23 Mar '23

23 Mar '23

Greetings, My name is Yuchen He, I'm a first year computer science student from Germany and I'm interested in the coreboot project as well as participating in Google Summer of Code. I'm interested in computer hardware and architecture and also low level programming, so I hope to learn more about these through a GSoC project. Some interesting projects I came across are: - Work on tools to extract register information from datasheets. (For Intel datasheets for instance) - A tool to generate vboot maps automatically - Add additional unit tests - Complete serialICE integration into coreboot but I wouldn't mind doing any other project. Best regards! :)

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coreboot March 2023