coreboot October 2023

coreboot@coreboot.org

29 participants
42 discussions

Feedback wanted for coreboot website update
by Matt DeVillier 03 Nov '23

03 Nov '23

Greetings coreboot community! One of the items to come out of OSFC and the previous leadership meeting was the need to overhaul coreboot's website to look more "professional" -- like a project which was used by commercial entities large and small, not just something for hobbyists/tinkerers. The leadership council has decided to move forward with this, and would like to hear from the coreboot community as part of developing requirements. These reqs roughly fall into 3 broad categories: logistical, aesthetic, and content. Some of the ideas been put out so far: [logistical] * Everything must be owned and run by coreboot - not an outside developer. * Everything must be contained in a git repo (outside of downloadable files like releases). * As much as possible should be generated statically? [aesthetic] * Use a site-wide top bar for navigation? (similar to https://www.zephyrproject.org) [content] * Prominent display of companies using coreboot (similar to https://go.dev) We'd love to hear from anyone else with ideas on how we can improve from the existing site. regards, Matt

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coreboot Meeting Annoucements And Agenda Call
by mina＠coreboot.org 31 Oct '23

31 Oct '23

Dear coreboot community, Please note that the coreboot leadership meeting is scheduled for Wednesday, November 1, 2023 [1]. You are welcome to add things you wish to see addressed during the meeting to the agenda [2]. ## Current Agenda Items: ### [Martin] Thoughts on enabling shallow clones of submodules by default? _.shallow_ _When set to true, a clone of this submodule will be performed as a shallow clone (with a history depth of 1) unless the user explicitly asks for a non-shallow clone._ ### [Martin] Slow down syncing of coreboot’s master branch to Daily? Weekly? We want not using the main branch to start being a little painful, without completely breaking things yet. We’ll want to discontinue updates to master and delete it in a month or two. ### [Matt] Requirements for new website * Everything must be owned and run by coreboot - not an outside developer. * Everything must be contained in a git repo (outside of downloadable files like releases). * As much as possible should be generated statically? * Use a site-wide top bar for navigation? ### [Martin] Should we have a separate meeting to discuss coreboot RFC patches? https://review.coreboot.org/q/status:open+repo:coreboot+message:rfc ### [Martin] RFC: util/sconfig: Add 'enable_option' keyword This will allow a Kconfig option to be used to enable/disable a device Do we also want a “disable_option” keyword that enables the device if it’s not set? Should we just make a 2nd Kconfig option that’s set when the first isn’t? * https://review.coreboot.org/c/coreboot/+/78604 ### [PatrickR] RFC on coreboot forms representation: * https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/PX6W… 5S/' * https://review.coreboot.org/c/coreboot/+/77882/ * https://review.coreboot.org/c/coreboot/+/74121/ * https://review.coreboot.org/c/coreboot/+/78506/ * https://review.coreboot.org/c/coreboot/+/78296/ * https://github.com/9elements/edk2/commit/f34f17996444ef811cc0223b4f875c45da… ### [Martin] Clang-format update - show the pros & cons. ### [Martin] 4.22 release scheduled for 2023_11_17 4.22 release checklist & meeting minutes Release meetings run for 4 weeks starting this friday. See the coreboot calendar for details. Discussions happen on IRC in #coreboot_releases [1] https://coreboot.org/calendar.html [2] https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK…

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coreboot interest, can a total notice create a new build?
by Steven Vervaecke 31 Oct '23

31 Oct '23

Hi, I recently started to delve into the coreboot world. I dont have any experience in firmware and i see that my laptop is currently not supported. Can i create a coreboot version for my laptop from scratch using this guide? https://doc.coreboot.org/tutorial/part1.html? Or is it not advised, not worth my time and should i ask a pro who is skilled at this? Regards, Steven V

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More details about Arbitrage? (tool to work with schematics programmatically)
by Paul Menzel 31 Oct '23

31 Oct '23

Dear coreboot folks, Today, in commit 952a4473ec23 (mb/google/brox: Add Arbitrage generated gpio.c file) [1], I first read consciously about the tool Arbitrage: > mb/google/brox: Add Arbitrage generated gpio.c file > > Checking in gpio.c generated by arbitrage. Used this command line to > generate: > arb export-coreboot-gpio --refdes=U1 brox:proto1_20231017 Commit dbc904b26768 (mb/google/brya/var/ghost: Add auto-generated GPIO config from Arbitrage) [2], I found, where the tool is mentioned the first time, includes a description: > Arbitrage is an internal tool at Google to work with schematics > programatically. In particular, it features an "export-coreboot-gpio" > command, which, does it's best to try and make a gpio.c from the > schematics to avoid human errors when translating to C code. It’d be great, if you could share more details, and if there are plans to make it public. Also, is that tool used to create `gpio.c` for all boards? Kind regards, Paul [1]: https://review.coreboot.org/c/coreboot/+/78657 [2]: https://review.coreboot.org/c/coreboot/+/65210

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AM4 Ryzen Port problem: timer irq issue maybe?
by Marty E. Plummer 31 Oct '23

31 Oct '23

Hello. I've been working on porting coreboot to Asrock X370 Killer Sli/AC, and I've made quite a lot of progress, and can even boot arch linux off usb from either seabios or tianocore. However, there's a number of odds and ends that need to be fixed which will require a lot of build/flash/boot cycles to wholly figure out. Problem is, the act of booting linux in my board's current state is an absolute chore to perform. After grub loads the kernel and initramfs, it goes quite smoothly for a while, but at some point, it slows to an absolute crawl/almost halts entirely. I've found that by plugging and unplugging a usb keyboard it causes the boot to progress a bit more each time, until it gets to the point where getty@ttyS0 comes up and sshd is running. Once ssh'd in, I can basically use it just like it was the vendor firmware, a few outstanding issues notwithstanding. This slowing/halting of boot also occurs if I issue a shutdown command and requires the same plug/unplug manipulation to make it actually finish. It has been suggested to me in a few places that its a lack of a timer irq getting through, but I'm not certain that's actually it but its the only lead I have to go on right now. My current state of code is at: https://review.coreboot.org/c/coreboot/+/77879 and is largely based off the zork chromebooks and the mandolin devel board's code. As I can see no particular handling of timer irqs in either I'm at a loss as to what could be the missing piece of the puzzle. Once I can build/flash/boot a bit faster I'm almost certain I can get the usb ports coming off the x370 chipset working (pcie and sata both appear to be fully functional as of this moment, more testing required) but as mentioned, it is *such a painful process* to actually boot linux on it in its current state. Any suggestions or solutions greatly appreciated. Regards, Marty

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Replacing BIOS
by R B 31 Oct '23

31 Oct '23

Dear Sir / Madam, I bought a mini PC with an N100 CPU and AMI BIOS on Aliexpress. Is it possible to replace the AMI BIOS with coreboot? Yours sincerely, Rachid. P.S. I read on the internet that Chinese equipment may be spying via devices/electronics. Is that true? And will changing BIOS help against this?

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coreboot Leadership Meeting
by mina＠coreboot.org 30 Oct '23

30 Oct '23

Dear coreboot Community, We are pleased to announce the upcoming coreboot leadership meeting scheduled for Wednesday, November 1, 2023.[1] Please feel free to add things you wish to see addressed during the meeting to the agenda.[2] [1] https://coreboot.org/calendar.html [2] https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK… 3tcg8b

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Compatibility
by Christopher Rigdon 30 Oct '23

30 Oct '23

Greetings, I was browsing you web site and saw that you have open source firmware for the Lenovo Thinkpad T430. I have an Ideapad Y430 and was wondering if it would be a compatible laptop as well? Your assistance is much appreciated. Thanks, -Chris Rigdon

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 29 Oct '23

29 Oct '23

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 4 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1523711: Memory - illegal accesses (BUFFER_SIZE) /src/mainboard/prodrive/hermes/mainboard.c: 114 in update_board_layout() ________________________________________________________________________________________________________ *** CID 1523711: Memory - illegal accesses (BUFFER_SIZE) /src/mainboard/prodrive/hermes/mainboard.c: 114 in update_board_layout() 108 /* Update CPU fields */ 109 for (struct device *cpu = all_devices; cpu; cpu = cpu->next) { 110 if (!is_enabled_cpu(cpu)) 111 continue; 112 layout.cpu_count++; 113 if (!layout.cpu_name[0]) >>> CID 1523711: Memory - illegal accesses (BUFFER_SIZE) >>> Calling "strncpy" with a maximum size argument of 50 bytes on destination array "layout.cpu_name" of size 50 bytes might leave the destination string unterminated. 114 strncpy(layout.cpu_name, cpu->name, sizeof(layout.cpu_name)); 115 } 116 117 if (cpuid_get_max_func() >= 0x16) 118 layout.cpu_max_non_turbo_frequency = cpuid_eax(0x16); 119 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Re: RFC: generating more ACPI tables at buildtime
by niewoehner.michael 29 Oct '23

29 Oct '23

Heh, once I had that idea as well when working with ACPI. This really would help when debugging stuff. The way I did it was dumping the generated ASL from the live OS and then loading overriding stuff through Linux' means (boot dsdt override + runtime patching). That somehow worked but wasn't really stable and reliable. ---- Am Sa, 28 Okt 2023 16:28:45 +0200 schrieb Matt DeVillier <mailto:matt.devillier@gmail.com> ---- Funnily enough I had this thought as well when I first started working with acpigen, but now that I've used it more, I definitely appreciate the ability to generate tables/device status etc at runtime based on the actual hardware. I definitely agree that having more asl / more build-time tables makes debugging easier. I think the idea of a userspace program that can generate a mock SSDT (and/or any other runtime-generated tables) based on assumed hardware presence would be great, that way we can inspect and debug the ssdt without having to boot actual hardware and dump it. It could even generate a config file with all the "toggleable" hardware and we could set the status to on/off and then use that for the mock table generation. And we could expand our ACPI checks to validate the mock tables (or just run them through iasl), which would allow us to improve our ACPI to better handle "picky" OSes like Windows. re: setting various enable bits (or ACPI _STA) at runtime: we've actually started doing that already for a lot of things in soc/amd/common, where the devices are generated by static asl and the _STA() method returns a variable (eg, STAT) which defaults to off (0x0) and if present is overridden in the SSDT (by setting STAT to 0xF). I'm not sure this is the ideal way of doing it, so would love to hear other ideas as well. On Sat, Oct 28, 2023 at 7:39 AM Arthur Heymans <mailto:arthur@aheymans.xyz> wrote: _______________________________________________ coreboot mailing list -- mailto:coreboot@coreboot.org To unsubscribe send an email to mailto:coreboot-leave@coreboot.org Hi Except the DSDT most ACPI tables are generated at runtime in coreboot. For some tables runtime generation is actually desirable like SSDT. For other tables a lot of the data is known at buildtime, which makes it possible to create them at buildtime and simply load them into memory at runtime. Having the tables generated at runtime makes them hard to debug and inspect or even validate. A few examples: - MCFG: everything is known at buildtime - FADT: only pointers to DSDT and FACS need updating. The rest is typically known at buildtime. - MADT: Currently all LAPICs are generated in SSDT and in MADT. Maybe this could be changed to swapping the enabled 'bits' at runtime but having the table there at buildtime? This could avoid the complicated code to deal with SMP threads sorting and Intels hybrid infrastructure that currently happens at runtime. - TMP log tables: only the pointer to the table needs updating. What do you think about creating a userspace program that takes most of the ramstage sources, mocks a few functions, creates some meaningful data input values to make it usable/executable in userspace and runs the ACPI generation code with it and outputs it into a file or even multiple files? Then the coreboot ramstage could just load those tables from cbfs instead of generating them. Some thoughts: - It could mean more maintenance as you likely want to keep both runtime and buildtime options available for most tables. - code size is reduced (good) in favor of larger data. I am not sure what the overall impact is on the boot medium footprint. - Having a way to generate tables at buildtime makes writing ACPI code easier. You don't need to run it on actual hardware to develop them, even if the end goal is to eventually generate things at runtime. Let me know what you think. Arthur _______________________________________________ coreboot mailing list -- mailto:coreboot@coreboot.org To unsubscribe send an email to mailto:coreboot-leave@coreboot.org

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coreboot October 2023