coreboot February 2020

coreboot@coreboot.org

40 participants
31 discussions

Re: F2A85-M - amdgpu fails, integrated GPU works fine
by Mike Banon 22 Jul '20

22 Jul '20

> Jan 12, 2020, 14:43 by mikebdp2(a)gmail.com: > > Solution for your coreboot + discrete GPU problems like > > amdgpu kernel bo map failed [...] error -22 > amdgpu_vram_scratch_init failed [...] error -22 > fatal error in GPU initialization > > It turned out that a fix like > https://review.coreboot.org/c/coreboot/+/38215 ( /* Set to 0xD0 > instead of 0xE0 to avoid the PCI resource allocation problems. */ > InitPost->MemConfig.BottomIo = 0xD0; // at the beginning of > board_BeforeInitPost function at board's OemCustomize.c ) that worked > for HD6670, is not enough for a huge RX590 - which is huge in all > relations, but most importantly the memory ranges! > > To get RX590 working with ASUS A88XM-E, I had to decrease a BottomIo > even further - to 0xC0 - and also to reduce the > BLDCFG_UMA_ALLOCATION_SIZE at board's buildOpts.c from 0x2000 (512MB) > to 0x1000 (256MB), - to get this extra "0xD0-0xC0"=0x10000000 room. > And then it worked perfectly, at least with DRI_PRIME=1 ./Supertuxkart > GPU offloading: ultra settings on integrated - 4 or 5 fps, with > offloading - 60 fps. I'm sure this fix will work for your other RX 5** > as well, but don't know if I should be trying to commit it to master, > since it lowers the integrated GPU's shared memory. > > RX590 is the most powerful AMD GPU which does not contain a Platform > Security Processor aka PSP (yes, they've started adding this crap to > the GPUs as well, and newer Vega / RX 5*** are all contaminated - see > for yourself at freedesktop drm/amdgpu sources) . That's why it was > really important to get RX590 working. So happy it was possible, > thanks to you all ;-) > > On Mon, Jan 13, 2020 at 2:21 AM Grzegorz Bogdał <bogdal.grzegorz(a)tutanota.com> wrote: > Great job!: ) So, A10-6800k/FX-8xxx combined with RX 590 is probably the strongest x86 desktop without PSP/ME that we'll get in this reality? Yes, if you meant x86 desktop "supported by coreboot master" - regarding the CPUs ;-) Otherwise there is a supported-by-coreboot-4.11 M5A88-V motherboard with AM3+ (maybe can put FX-9590 there, if coreboot supports and without frying it?) and KGPE-D16 with its' two Opterons 6386 SE for a large desktop. Also, PDF [link 1] at page 12 says Carrizo is the "1st ARM Trustzone Capable Performance APU", that means Kaveri and its' refresh Godavari (i.e. A10-7890K) doesn't have a PSP. A88XM-E motherboard is FM2+ socket, so theoretically it could support Godavari A10-7890K. However Balazs wrote that AGESA of Kaveri is a blob (not good!) and there's uncertainty if could get it working without getting this APU for trying. As you see, there are CPUs more powerful than A10-6800K which don't have a PSP crap but their coreboot master support is questionable. And don't want to be without coreboot, since UEFI could have many holes and stuff like Computrace which doesn't need to rely on ME/PSP to function. So yes, A10-6800K seems to be the best at the moment. I got A10-6700 only because its' quite hard to find a new A10-6800K for a reasonable price and I read about bad overclockers who played too much with core voltages and cores deteriorate, becoming unstable even at stock speeds (so one needs to underclock then). A10-6700 is the most powerful with a locked multiplier, so less attractive to overclockers and may be safer to buy used. GPUs: yes, RX590 is the most powerful GPU without PSP ! (not considering NVidia at all because of their proprietary driver tricks and hostility towards the opensource) . Although there is RX600 series [link 2], they are hard to buy and lower performance. Unlike the majority of people (who don't care about performance), I actually hoped there would be another refresh of Polaris architecture - simply because no PSP, but doesn't seem there would be more Polaris high end GPUs at the moment. As for the most powerful RX590, I suggest those which have 8400MHz memory by default - i.e. Sapphire Nitro+ parts. For myself I got a cute [link 3] SKU 11289-07-20G aka "Sapphire Nitro+ RX 590 8GB AMD 50th Anniversary Gold Edition" (golden shroud) for about 250 USD. Aside from being an AMD fanboy collector's item, it's nearly identical to 11289-01-20G aka "Special Edition" (blue shroud) - however, there were multiple hardware revisions of a Special Edition card (could be distinguished by looking at their advanced P/N product number also printed), while this Gold Edition came much later and with it I think you're guaranteed to get the latest hardware revision. Now they are sold out at many countries, but if you're lucky you could find some - although maybe for the really inflated prices like [link 4] - that's ~320, about 30% more than I paid. If you know another RX590 which is more powerful out of the box, please tell - maybe I'd get a second one! In example, here's a pretty [link 5] PowerColor Red Devil RX 590 8GB, with a neat pentagram on its' back plate ;-) But its' memory is 8000MHz by default. [1] https://github.com/mikebdp2/coreboot-related/blob/master/PHILIPPINES_PS-DBM… [2] https://en.wikipedia.org/wiki/Radeon_600_series [3] https://www.sapphiretech.com/en/consumer/nitro-rx-590-8g-g5_gold_edition [4] 133178207205 - https://www.ebay.com/itm/SAPPHIRE-AMD-RADEON-RX-590-NITRO-AMD50-GOLD-EDITIO… [5] https://www.powercolor.com/product?id=1542008942

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Extended IvyBridge CPU configuration
by Lars Hochstetter 16 Jul '20

16 Jul '20

Hi everyone, I'm looking for an option to configure my Intel IvyBridge CPU (enable / disable Hyperthreading, TurboBoost, set configurable TDP level etc.) using coreboot / nvramcui. My board is a Lenovo Thinkpad T430. So far, "only virtualization" is configurable and can not be enabled / disabled "in flight" but requires a rebuild of coreboot. Is anyone currently working on something similar? Is anything planned in that regard? Kind regards lhochstetter

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Booting Linux kernel with nosmp required on Lenovo T60 (ATI/AMD)
by Paul Menzel 07 Jul '20

07 Jul '20

Dear coreboot folks, On the Lenovo T60 (with AMD/ATI graphics) the Linux kernel (4.9, 4.19, 5.3, 5.4) hangs after starting user space. As SeaBIOS, GRUB, payloads and FreeDOS work, I tried to limit the number of CPUs, and booting Linux with `nosmp` gave me a booting system. It worked with older coreboot versions, so I think it’s a regression. I am able to reproduce this with coreboot 4.11 and 4.11-422-g1a5c3bb7fa. Is somebody else seeing this issue? Maybe on some i945 desktop board, so it would be easier to bisect? Kind regards, Paul

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OpenBSD won't install on an x220 Thinkpad with Coreboot
by Robert Milton 12 Apr '20

12 Apr '20

I'm trying to get OpenBSD to install on an x220 Thinkpad with Coreboot/SeaBIOS but I'm running into two problems: the ethernet device doesn't work and OpenBSD doesn't detect my HDD. dmesg said em0 wouldn't load because the EEPROM had an invalid signature. I have no idea why OpenBSD doesn't see my HDD though. It's strange because everything works fine under Linux. And I cannot seem to mount a usb drive under the OpenBSD installer to attach dmesg errors. I originally posted this as a bug report to bug report mailing list but Theo said it would be better suited for Coreboot's and wasn't a bug in OpenBSD.

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Mainboard porting assistance
by Benjamin Doron 10 Apr '20

10 Apr '20

Hi all, I own an Acer Aspire VN7-572G and have not been impressed with its OEM firmware. After discovering that it does not utilise Intel's Boot Guard technology, that several Skylake and Kabylake laptops (it has a Skylake chip, but I read that the platforms are similar) have received successful coreboot ports and reading the porting guide on the wiki, I figured that I could give porting coreboot to my laptop a shot. When I was done, I figured that I had an image that might boot so I flashed it to my laptop with a Raspberry Pi and a SOIC clip. However, here's what it does: a) It powers on quietly, as expected; b) The backlight and power LED light up; c) The fans spin up to high and then it stays that way. It does nothing else. The display is dark too. After 15 minutes and a second attempt, I figured that I could no longer blame anything on a long first boot-up and gave up and flashed back to stock. Now, in all honesty I should have tried first without cleaning Intel ME but I find it so much more likely that I did something wrong than that cleaning ME was the sole problem. Can anyone advise me on how to continue? My code is here: https://github.com/benjamindoron/coreboot

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Status of Optimus work? Target laptops?
by Matt B 04 Mar '20

04 Mar '20

Hi, As I understand it, the only thing missing with regard to nvidia dGPUs on Coreboot are the ACPI calls to turn them on and off at run-time, which is what Optimus is. Things like DRI_PRIME and similar work just fine as long as the dGPU is running, even under nouveau. What is the current status of the work to get nvidia Optimus working? From what I gather there have been a couple of attempts and a recent restart, but I don't know what the current status of this work is. I have heard that some laptops currently have the option to switch the dGPU on or off at boot-time. For which ones does this work? If the work on Optimus is completed, what laptops are most likely to support it? My expectation is that turning the GPU on or off may be different for different laptops, even though the ACPI calls are the same, and so may not work everywhere. Thanks, -Matt

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Still need assistance porting to ASUS P8Z77-M
by Keith Hui 01 Mar '20

01 Mar '20

A week ago I wrote here about my problems trying to port coreboot to my board. Unfortunately I am still no closer to booting. In the meantime I flashed my new chip with my OEM firmware backup. It boots; then I flashed my patched IFD (for chip ID and flash unlock) and it still boots. So it's not chip compatibility or corrupted descriptor. The only sign of life I got is the bootblock banner left in the SPI console. My PCI POST card is showing nothing, but knowing that it sits on a PCIe-PCI bridge (ASM1063 that P8Z77M-PRO does not have) and not knowing if it needs software init to work, I am now trying to pull POST codes off the LPC bus over the TPM header, using an Arduino Due. Do I have to add some early init to have port 80 accesses sent to LPC bus for this to work? Thanks for your help Keith

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Xeon SP code structure
by Andrey Petrov 28 Feb '20

28 Feb '20

Dear coreboot folks, As some you know we at OSF are working on enabling Xeons in coreboot. We have recently uploaded Skylake-SP which goes in src/soc/intel/skylake_sp. At the same time we are working on enabling next generation SP processor. I was wondering what may be a good way to structure the code. It feels wrong to just throw code into src/soc/intel especially for systems with discrete PCH. I'd like to hear opinions and discuss what may be a good way to structure and organize the code. Here is what we want to achieve: * Make code modular It looks like certain things are similar to all -SP variants and it makes sense to share that code rather than copy-paste. * Allow same motherboard to host different CPU (and potentially different PCH) The practical thing here is that some server boards support two generations of CPUs that are pin-compatible. However, chip code is different. PCH may be same or different. * Did I already say eliminate/decrease copy-pasta? Here is a structure that I came up with so far (patch stack ending with 39017) cpu/xeon_sp/ ├─ Kconfig # baseline of config ├─ include/ # common headers ├─ common/ # true common code such as IIO stacks code, ACPI tables ├─ cpu/skylake-sp/ │ ├─ include/ # cpu/northbridge defines specific to given model │ ├─ Kconfig # whatever overrides from common we need │ └─ *.c # code that implements specific platform bits ├─ cpu/nextlake-sp/ │ ├─ include/ # same │ ├─ Kconfig # same │ └─ *.c # same Now then, the "common" xeon_sp code may be placed in src/northbridge. We probably should add Lewisburg C62x code in src/southbridge as well. Thoughts? Alternatively, we can place everything in soc/intel/ and put Xeon server common code in soc/intel/common/block/ or similar. This may be easiest way but fells messy. Is there any other way with pros and cons? thanks Andrey

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Coreboot for Minnowboard MAX-A2
by Sathish Kumar Balasubramaniam -ERS, HCL Tech 27 Feb '20

27 Feb '20

Hi All, To build Coreboot on Minnowboard MAX - A2, is the following link the updated one or any other latest steps ? https://elinux.org/Minnowboard:MinnowMaxCoreboot Regards, B.Sathish Kumar ::DISCLAIMER:: ________________________________ The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted, lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents (with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates. Views or opinions, if any, presented in this email are solely those of the author and may not necessarily reflect the views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of authorized representative of HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. Before opening any email and/or attachments, please check them for viruses and other defects. ________________________________

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Prospective GSoC 2020
by Harshavardhan Unnibhavi 26 Feb '20

26 Feb '20

Hi, I am Harshavardhan Unnibhavi, a first year PhD student at the University of Edinburgh, working in security and storage systems. I am interested in contributing to Coreboot through GSoC 2020 program. I am interested in the project to Learn hardware behavior from IO and memory access logs. The project ideas page doesn't have a very good description of how to get started. Hence I have a few questions: 1) What contributions, if any, are required to get selected to work on this project? 2) I am comfortable with C, Python, Git and have a decent amount of machine learning experience as well. What other skills do I need? I have a decent knowledge of how the driver works to access hardware resources. Any other things I should be aware of? Looking forward to hearing from you. Best, Harshavardhan Unnibhavi

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coreboot February 2020