coreboot July 2019

coreboot@coreboot.org

39 participants
48 discussions

Re: Question about blobs
by Jorge Fernandez Monteagudo 03 Jul '19

03 Jul '19

Hi again, A clarification. From the StoneyPI_1_3_0_A.ZIP file I've got under NDA is it possible to compile it and get the AGESA.bin file? For instance, for the fam15tn family the coreboot build process generates a libagesa.fam15tn.a file which is integrated in the final coreboot.rom file. Could it be possible to do the same from a PI family? The build process in coreboot is only prepared to use a wrapper and the AGESA.bin file, but maybe is it possible to generate the AGESA.bin from the zip file... Thanks! ________________________________ De: Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com> Enviado: martes, 2 de julio de 2019 14:25 Para: Kyösti Mälkki Cc: coreboot(a)coreboot.org Asunto: [coreboot] Re: Question about blobs Hi Kyösti! Thanks for the info! >AMD contracted SilverBack for the tasks on StoneyRidge (and >MerlinFalcon apparently). The source is a heavily modified StoneyPI >package. You may get the unmodified one from AMD reps under NDA. Or >pay SilverBack for the development you would be more capable of doing >yourself, and you still might not get a license that allows >distributing the work. There was a promise of scrubbing and >relicensing StoneyPI source but... Let's just say legalities messed it >up, I don't have the details. Yes, the AMD reps we're in touch answer me to get in touch with SilverBack to get support :( We've been able to get a more recent StoneyPI_1_3_0_A.ZIP under NDA because I've seen this version fixed the issue: EMBSWDEV-4487: System is not booting when memory is connected only to DIMM 1 slot maybe related with our problem, but I don't know how to integrate this code into coreboot... And if you say that the current work in coreboot is from a heavily modified base from SilverBack I don't have any chance to make it work... >As for the the other blobs (MullinsPI, CarrizoPI, KaveriPI), those >were either built at SAGE (R.I.P.) or AMD AES (R.I.P.) and I have been >told the repositories and toolchains were never officially transferred >to SilverBack's possession. In other words, even if you paid, >SilverBack is not likely to work on those. Then, no more options to get a working BIOS than SilverBack? >I believe we have talked before. Maybe it was about CarrizoPI? I was >asking for commercial adopters around coreboot and binaryPI, in >attempts to get to the same negotiation table with AMD management. Did >You or Your manager ever respond? Yes. I began asking in the coreboot mailing list about the Bettong mainboard. I added TPM support and tianocore to that demoboard. I remember the email and I answered it giving my support because we thought coreboot is the way to go to support our custom board. Regards, Jorge

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Re: Does Coreboot support the following options to enable/disable?
by Ashmita Chakraborty 03 Jul '19

03 Jul '19

Hi Ranga, Exactly, only Hyperthreading is available. I could not find Intel Virtualization Tech , MLC streamer, etc. So here's my question if all these options support coreboot for Xeon D-15xx? Thanks&Regards, Ashmita Chakraborty ________________________________ From: Ranga Rao <rangarao(a)ircona.com> Sent: Wednesday, July 3, 2019 1:15:07 PM To: Ashmita Chakraborty; coreboot(a)coreboot.org Subject: RE: [coreboot] Re: Does Coreboot support the following options to enable/disable? Hi Ashmita, I could see HyperThreading Enable/Disable in Upd_Data_region FSP-master\BroadwellDEFspBinPkg\include\fspvpd.h Regards Ranga From: Ranga Rao <rangarao(a)ircona.com> Sent: Wednesday 3 July 2019 08:18 To: Ashmita Chakraborty <Ashmita.Chakraborty(a)Ltts.com>; coreboot(a)coreboot.org Subject: [coreboot] Re: Does Coreboot support the following options to enable/disable? Hi Ashmita, Broadwell-DE / Xeon D support still depends Intel's closed-source FSP (Firmware Support Package) binary-only blobs. Broadwell-DE SoC / Xeon D Support Added To Coreboot Hope you could configure them through fsp_upd_data? Regards Ranga From: Ashmita Chakraborty <Ashmita.Chakraborty(a)Ltts.com<mailto:Ashmita.Chakraborty@Ltts.com>> Sent: Wednesday 3 July 2019 08:14 To: Ranga Rao <rangarao(a)ircona.com<mailto:rangarao@ircona.com>>; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Does Coreboot support the following options to enable/disable? Dear Ranga, These options are meant for Xeon D-15xx series family. So will the coreboot support these options? The coreboot will be built for Xeon D-15xx processor. Yes, I have access to them in fsp_early_init through fsp_upd_data. Thanks&Regards, Ashmita Chakraborty ________________________________ From: Ranga Rao <rangarao(a)ircona.com<mailto:rangarao@ircona.com>> Sent: Tuesday, July 2, 2019 8:41 PM To: Ashmita Chakraborty; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] Does Coreboot support the following options to enable/disable? Hi, As these features are processor/SoC specific and they are part of FSPM, they should be configurable during fsp early init in coreboot, though you may not find a KConfig option to enable/disable Do you have access to them in fsp_early_init through fsp_upd_data? Regards Ranga -----Original Message----- From: ashmita.chakraborty(a)ltts.com<mailto:ashmita.chakraborty@ltts.com> <ashmita.chakraborty(a)ltts.com<mailto:ashmita.chakraborty@ltts.com>> Sent: Tuesday 2 July 2019 07:34 To: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: [coreboot] Does Coreboot support the following options to enable/disable? Does the coreboot support the following options to enable/disable: HyperThreading - Disabled Execute Disable Bit - Enabled Intel Virtualization Tech- Enabled Intel (R) TXT- Disabled Enhanced Error Containment Mode -Disabled MLC Streamer -Enabled MLC Spatial Prefetcher -Enabled DUC Data Prefetcher -Enabled DUC Instruction Prefetcher -Enabled LLC Prefetch - Enabled Intel Configurable TDB -Enabled TDP Level -level 2 Please let me know. Thanks in advance. Regards, Ashmita Chakraborty _______________________________________________ coreboot mailing list -- coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> To unsubscribe send an email to coreboot-leave(a)coreboot.org<mailto:coreboot-leave@coreboot.org> L&T Technology Services Ltd www.LTTS.com<http://www.LTTS.com> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. L&T Technology Services Ltd www.LTTS.com This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: Does Coreboot support the following options to enable/disable?
by Ranga Rao 03 Jul '19

03 Jul '19

Hi Ashmita, I could see HyperThreading Enable/Disable in Upd_Data_region FSP-master\BroadwellDEFspBinPkg\include\fspvpd.h Regards Ranga From: Ranga Rao <rangarao(a)ircona.com> Sent: Wednesday 3 July 2019 08:18 To: Ashmita Chakraborty <Ashmita.Chakraborty(a)Ltts.com>; coreboot(a)coreboot.org Subject: [coreboot] Re: Does Coreboot support the following options to enable/disable? Hi Ashmita, Broadwell-DE / Xeon D support still depends Intel's closed-source FSP (Firmware Support Package) binary-only blobs. Broadwell-DE SoC / Xeon D Support Added To Coreboot Hope you could configure them through fsp_upd_data? Regards Ranga From: Ashmita Chakraborty <Ashmita.Chakraborty(a)Ltts.com<mailto:Ashmita.Chakraborty@Ltts.com>> Sent: Wednesday 3 July 2019 08:14 To: Ranga Rao <rangarao(a)ircona.com<mailto:rangarao@ircona.com>>; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: Re: [coreboot] Does Coreboot support the following options to enable/disable? Dear Ranga, These options are meant for Xeon D-15xx series family. So will the coreboot support these options? The coreboot will be built for Xeon D-15xx processor. Yes, I have access to them in fsp_early_init through fsp_upd_data. Thanks&Regards, Ashmita Chakraborty ________________________________ From: Ranga Rao <rangarao(a)ircona.com<mailto:rangarao@ircona.com>> Sent: Tuesday, July 2, 2019 8:41 PM To: Ashmita Chakraborty; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] Does Coreboot support the following options to enable/disable? Hi, As these features are processor/SoC specific and they are part of FSPM, they should be configurable during fsp early init in coreboot, though you may not find a KConfig option to enable/disable Do you have access to them in fsp_early_init through fsp_upd_data? Regards Ranga -----Original Message----- From: ashmita.chakraborty(a)ltts.com<mailto:ashmita.chakraborty@ltts.com> <ashmita.chakraborty(a)ltts.com<mailto:ashmita.chakraborty@ltts.com>> Sent: Tuesday 2 July 2019 07:34 To: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: [coreboot] Does Coreboot support the following options to enable/disable? Does the coreboot support the following options to enable/disable: HyperThreading - Disabled Execute Disable Bit - Enabled Intel Virtualization Tech- Enabled Intel (R) TXT- Disabled Enhanced Error Containment Mode -Disabled MLC Streamer -Enabled MLC Spatial Prefetcher -Enabled DUC Data Prefetcher -Enabled DUC Instruction Prefetcher -Enabled LLC Prefetch - Enabled Intel Configurable TDB -Enabled TDP Level -level 2 Please let me know. Thanks in advance. Regards, Ashmita Chakraborty _______________________________________________ coreboot mailing list -- coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> To unsubscribe send an email to coreboot-leave(a)coreboot.org<mailto:coreboot-leave@coreboot.org> L&T Technology Services Ltd www.LTTS.com<http://www.LTTS.com> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: Does Coreboot support the following options to enable/disable?
by Ashmita Chakraborty 03 Jul '19

03 Jul '19

Hi Ranga, Yes, Xeon D depends on Intels's FSP. I have explored that the coreboot will be built on Xeon D but I am not confident enough that those options could be configured through fsp_upd_data. Thanks&Regards, Ashmita Chakraborty ________________________________ From: Ranga Rao <rangarao(a)ircona.com> Sent: Wednesday, July 3, 2019 12:47:59 PM To: Ashmita Chakraborty; coreboot(a)coreboot.org Subject: RE: [coreboot] Does Coreboot support the following options to enable/disable? Hi Ashmita, Broadwell-DE / Xeon D support still depends Intel's closed-source FSP (Firmware Support Package) binary-only blobs. Broadwell-DE SoC / Xeon D Support Added To Coreboot Hope you could configure them through fsp_upd_data? Regards Ranga From: Ashmita Chakraborty <Ashmita.Chakraborty(a)Ltts.com> Sent: Wednesday 3 July 2019 08:14 To: Ranga Rao <rangarao(a)ircona.com>; coreboot(a)coreboot.org Subject: Re: [coreboot] Does Coreboot support the following options to enable/disable? Dear Ranga, These options are meant for Xeon D-15xx series family. So will the coreboot support these options? The coreboot will be built for Xeon D-15xx processor. Yes, I have access to them in fsp_early_init through fsp_upd_data. Thanks&Regards, Ashmita Chakraborty ________________________________ From: Ranga Rao <rangarao(a)ircona.com<mailto:rangarao@ircona.com>> Sent: Tuesday, July 2, 2019 8:41 PM To: Ashmita Chakraborty; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] Does Coreboot support the following options to enable/disable? Hi, As these features are processor/SoC specific and they are part of FSPM, they should be configurable during fsp early init in coreboot, though you may not find a KConfig option to enable/disable Do you have access to them in fsp_early_init through fsp_upd_data? Regards Ranga -----Original Message----- From: ashmita.chakraborty(a)ltts.com<mailto:ashmita.chakraborty@ltts.com> <ashmita.chakraborty(a)ltts.com<mailto:ashmita.chakraborty@ltts.com>> Sent: Tuesday 2 July 2019 07:34 To: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: [coreboot] Does Coreboot support the following options to enable/disable? Does the coreboot support the following options to enable/disable: HyperThreading - Disabled Execute Disable Bit - Enabled Intel Virtualization Tech- Enabled Intel (R) TXT- Disabled Enhanced Error Containment Mode -Disabled MLC Streamer -Enabled MLC Spatial Prefetcher -Enabled DUC Data Prefetcher -Enabled DUC Instruction Prefetcher -Enabled LLC Prefetch - Enabled Intel Configurable TDB -Enabled TDP Level -level 2 Please let me know. Thanks in advance. Regards, Ashmita Chakraborty _______________________________________________ coreboot mailing list -- coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> To unsubscribe send an email to coreboot-leave(a)coreboot.org<mailto:coreboot-leave@coreboot.org> L&T Technology Services Ltd www.LTTS.com This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. L&T Technology Services Ltd www.LTTS.com This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: Does Coreboot support the following options to enable/disable?
by Ranga Rao 03 Jul '19

03 Jul '19

Hi Ashmita, Broadwell-DE / Xeon D support still depends Intel's closed-source FSP (Firmware Support Package) binary-only blobs. Broadwell-DE SoC / Xeon D Support Added To Coreboot Hope you could configure them through fsp_upd_data? Regards Ranga From: Ashmita Chakraborty <Ashmita.Chakraborty(a)Ltts.com> Sent: Wednesday 3 July 2019 08:14 To: Ranga Rao <rangarao(a)ircona.com>; coreboot(a)coreboot.org Subject: Re: [coreboot] Does Coreboot support the following options to enable/disable? Dear Ranga, These options are meant for Xeon D-15xx series family. So will the coreboot support these options? The coreboot will be built for Xeon D-15xx processor. Yes, I have access to them in fsp_early_init through fsp_upd_data. Thanks&Regards, Ashmita Chakraborty ________________________________ From: Ranga Rao <rangarao(a)ircona.com<mailto:rangarao@ircona.com>> Sent: Tuesday, July 2, 2019 8:41 PM To: Ashmita Chakraborty; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: RE: [coreboot] Does Coreboot support the following options to enable/disable? Hi, As these features are processor/SoC specific and they are part of FSPM, they should be configurable during fsp early init in coreboot, though you may not find a KConfig option to enable/disable Do you have access to them in fsp_early_init through fsp_upd_data? Regards Ranga -----Original Message----- From: ashmita.chakraborty(a)ltts.com<mailto:ashmita.chakraborty@ltts.com> <ashmita.chakraborty(a)ltts.com<mailto:ashmita.chakraborty@ltts.com>> Sent: Tuesday 2 July 2019 07:34 To: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: [coreboot] Does Coreboot support the following options to enable/disable? Does the coreboot support the following options to enable/disable: HyperThreading - Disabled Execute Disable Bit - Enabled Intel Virtualization Tech- Enabled Intel (R) TXT- Disabled Enhanced Error Containment Mode -Disabled MLC Streamer -Enabled MLC Spatial Prefetcher -Enabled DUC Data Prefetcher -Enabled DUC Instruction Prefetcher -Enabled LLC Prefetch - Enabled Intel Configurable TDB -Enabled TDP Level -level 2 Please let me know. Thanks in advance. Regards, Ashmita Chakraborty _______________________________________________ coreboot mailing list -- coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> To unsubscribe send an email to coreboot-leave(a)coreboot.org<mailto:coreboot-leave@coreboot.org> L&T Technology Services Ltd www.LTTS.com This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: Does Coreboot support the following options to enable/disable?
by Ashmita Chakraborty 03 Jul '19

03 Jul '19

Dear Ranga, These options are meant for Xeon D-15xx series family. So will the coreboot support these options? The coreboot will be built for Xeon D-15xx processor. Yes, I have access to them in fsp_early_init through fsp_upd_data. Thanks&Regards, Ashmita Chakraborty ________________________________ From: Ranga Rao <rangarao(a)ircona.com> Sent: Tuesday, July 2, 2019 8:41 PM To: Ashmita Chakraborty; coreboot(a)coreboot.org Subject: RE: [coreboot] Does Coreboot support the following options to enable/disable? Hi, As these features are processor/SoC specific and they are part of FSPM, they should be configurable during fsp early init in coreboot, though you may not find a KConfig option to enable/disable Do you have access to them in fsp_early_init through fsp_upd_data? Regards Ranga -----Original Message----- From: ashmita.chakraborty(a)ltts.com <ashmita.chakraborty(a)ltts.com> Sent: Tuesday 2 July 2019 07:34 To: coreboot(a)coreboot.org Subject: [coreboot] Does Coreboot support the following options to enable/disable? Does the coreboot support the following options to enable/disable: HyperThreading - Disabled Execute Disable Bit - Enabled Intel Virtualization Tech- Enabled Intel (R) TXT- Disabled Enhanced Error Containment Mode -Disabled MLC Streamer -Enabled MLC Spatial Prefetcher -Enabled DUC Data Prefetcher -Enabled DUC Instruction Prefetcher -Enabled LLC Prefetch - Enabled Intel Configurable TDB -Enabled TDP Level -level 2 Please let me know. Thanks in advance. Regards, Ashmita Chakraborty _______________________________________________ coreboot mailing list -- coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> To unsubscribe send an email to coreboot-leave(a)coreboot.org<mailto:coreboot-leave@coreboot.org> L&T Technology Services Ltd www.LTTS.com This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: Question about blobs
by Kyösti Mälkki 02 Jul '19

02 Jul '19

On Tue, Jul 2, 2019 at 1:01 PM Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com> wrote: > > Hi all, > > I would like to know the source of the AGESA.bin blobs I've seen in the 3rdparty directory. For instance, the '3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin'. Is it generated by AMD? Is it compiled from a NDA file by a coreboot developer? AMD contracted SilverBack for the tasks on StoneyRidge (and MerlinFalcon apparently). The source is a heavily modified StoneyPI package. You may get the unmodified one from AMD reps under NDA. Or pay SilverBack for the development you would be more capable of doing yourself, and you still might not get a license that allows distributing the work. There was a promise of scrubbing and relicensing StoneyPI source but... Let's just say legalities messed it up, I don't have the details. As for the the other blobs (MullinsPI, CarrizoPI, KaveriPI), those were either built at SAGE (R.I.P.) or AMD AES (R.I.P.) and I have been told the repositories and toolchains were never officially transferred to SilverBack's possession. In other words, even if you paid, SilverBack is not likely to work on those. I believe we have talked before. Maybe it was about CarrizoPI? I was asking for commercial adopters around coreboot and binaryPI, in attempts to get to the same negotiation table with AMD management. Did You or Your manager ever respond? Kyösti

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Question about blobs
by Jorge Fernandez Monteagudo 02 Jul '19

02 Jul '19

Hi all, I would like to know the source of the AGESA.bin blobs I've seen in the 3rdparty directory. For instance, the '3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin'. Is it generated by AMD? Is it compiled from a NDA file by a coreboot developer? Thanks! Jorge

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coreboot July 2019