coreboot April 2019

coreboot@coreboot.org

56 participants
48 discussions

Removal of mainboard Intel/Strago
by Nico Huber 15 Apr '19

15 Apr '19

Hi all, I just noticed that there is a seemingly abandoned board that creates a lot of maintenance burden for coreboot, also because it's using FSP UPDs that are not present in the upstream header files. Does anybody still care about Intel/Strago? If not, I'd prefer to drop it immediately. It's only a reference board, so likely never had many users. If somebody at Intel still cares about coreboot support for this board, please have a look at this issue [1]. Nico [1] https://github.com/IntelFsp/FSP/issues/14

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coreboot + Windows 3.1 payload
by John DeGood 14 Apr '19

14 Apr '19

Cute use of coreboot + SeaBIOS virtual floppy to run Windows 3.1 + apps from flash: https://sakamoto.pl/weblog/07-windows-3-flash-edition/ Reposted by Hackaday: https://hackaday.com/2019/04/10/windows-3-1-in-my-bios-its-more-likely-than…

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Re: Intel Leaf Hill Coreboot Trouble
by abujan＠msa.com.ar 12 Apr '19

12 Apr '19

Hi Cameron, I contact you since I am doing the same development as you. In my company we developed a board based on Leaf-hill CRB from Intel. I am in the process of making a clean image of the bios and I find the following problem to see if you can help me. Complete all the process that you comment having the account the last files of this year: Coreboot: V4.9 FSP: Intel MR5 (566285) IFWI image: "Intel-atome-e3900-soc-ifwi-224-41-release-package" (I think it is the last one available). Inside it has a ready-to-record image in 8Mb SPI. Do you know why most of the documents have 8mb images when the CRB that I have and my mother has 16Mb? The Flash description is extracted from the image that the CRB originally has with the tool "ifdtool.c". it is right? Well with these elements I configure coreboot using "menuconfig" as you mentioned in your post, at first I had an error compiling because I did not choose to use the BLOBS repo that it has in this version. Is that configuration fine? Finally, I managed to buid but at the end the following legend appears: """ This image contains the following sections that can be manipulated with this tool: 'SI_DESC' (size 4096, offset 0) 'IFWI' (size 3141632, offset 4096) 'COREBOOT' (CBFS, size 12703744, offset 3147776) 'RECOVERY_MRC_CACHE' (size 65536, offset 15851520) 'RW_MRC_CACHE' (size 65536, offset 15917056) 'RW_VAR_MRC_CACHE' (size 4096, offset 15982592) 'BIOS_UNUSABLE' (size 262144, offset 15986688) 'DEVICE_EXTENSION' (size 520192, offset 16248832) 'UNUSED_HOLE' (size 4096, offset 16773120) It is possible to perform either the write action or the CBFS add/remove actions on every section listed above. To see the image's read-only sections as well, rerun with the -w option. CBFSPRINT coreboot.rom FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 34116 none cpu_microcode_blob.bin 0x8600 microcode 46080 none fallback/ramstage 0x13a80 stage 76438 none config 0x26580 raw 304 none revision 0x26700 raw 673 none fallback/postcar 0x26a00 stage 16680 none fallback/dsdt.aml 0x2ab80 raw 5581 none fallback/payload 0x2c1c0 simple elf 67427 none payload_config 0x3c980 raw 1637 none payload_revision 0x3d040 raw 235 none (empty) 0x3d180 null 12420632 none bootblock 0xc157c0 bootblock 32768 none Built intel/leafhill (Leafhill) Image written successfully to build/cbfs/fallback/ifwi.bin.tmp. Image does not contain sub-partition OBBP(6). Sub-partition IBBP(4) entry IBBL replaced from file build/cbfs/fallback/bootblock.bin. Image written successfully to build/cbfs/fallback/ifwi.bin.tmp. W: Written area will abut bottom of target region: any unused space will keep its current contents ** WARNING ** coreboot has been built without an Intel Firmware Descriptor. Never write a complete coreboot.rom without an IFD to your board's flash chip! You can use flashrom's IFD or layout parameters to flash only to the BIOS region. """ To you this warning happens, because of that the .bin is not generated to download in the SPI memory. Can you help me with this situation? Thank you

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 12 Apr '19

12 Apr '19

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1400679: Incorrect expression (COPY_PASTE_ERROR) /src/arch/x86/smbios.c: 653 in smbios_write_type7() ________________________________________________________________________________________________________ *** CID 1400679: Incorrect expression (COPY_PASTE_ERROR) /src/arch/x86/smbios.c: 653 in smbios_write_type7() 647 t->max_cache_size = max_cache_size / KiB; 648 t->max_cache_size2 = t->max_cache_size; 649 650 t->max_cache_size |= SMBIOS_CACHE_SIZE_UNIT_1KB; 651 t->max_cache_size2 |= SMBIOS_CACHE_SIZE2_UNIT_1KB; 652 } else { >>> CID 1400679: Incorrect expression (COPY_PASTE_ERROR) >>> "cache_size" in "cache_size < 2147418112UL" looks like a copy-paste error. 653 if (cache_size < (SMBIOS_CACHE_SIZE_MASK * 64 * KiB)) 654 t->max_cache_size = max_cache_size / (64 * KiB); 655 else 656 t->max_cache_size = SMBIOS_CACHE_SIZE_OVERFLOW; 657 t->max_cache_size2 = max_cache_size / (64 * KiB); 658 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Hyperkitty mailing lists: cant get any attachments because of "<memory at 0x***>" errors
by Mike Banon 11 Apr '19

11 Apr '19

For example, I would like to download my advanced_bootmenu SeaBIOS patch that is attached to this message: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CKWLNT… Here is a direct link to the attachment that is provided by Hyperkitty web interface: https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/message/CKWLN… However, when I try to download it (tried both Firefox and wget) - instead of 13KB file it always gets 26 bytes. This is an ASCII error message: "<memory at 0x7f696b2a54c8>", "<memory at 0x7f696b2a51c8>" and so on. Maybe a segmentation fault somewhere? P.S. I miss the old Pipermail: with its' convenient old school web UI, short clear links and working attachments... :P Best regards, Mike Banon

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Do you know really useful SeaBIOS patches that have not been merged yet?
by Mike Banon 10 Apr '19

10 Apr '19

If yes, please tell me about them and I could either take them over (to try to get them merged after some changes) or add them to my SeaBIOS patching script: https://review.coreboot.org/c/coreboot/+/32238 Currently it contains two of my patches: 1) advanced_bootmenu.patch - NEW! [PATCH] advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CKWLNT… 2) multiple_floppies.patch [PATCH v2] ramdisk: search for all available floppy images instead of one https://mail.coreboot.org/pipermail/seabios/2018-December/012670.html (old mailing list links are prettier and its' attachments are supported by wget) I hope to get them merged eventually, but some people need them right now... So uploaded to Gerrit, they could be easily installed to coreboot with this script: https://pastebin.com/raw/hv9sSuMU I will also try searching the mailing list archives for these patches. Remember seeing at least one useful patch from someone else... Best regards, Mike Banon

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Please inform me about C100PA.
by 鈴木勝 10 Apr '19

10 Apr '19

Hello, this is my first post here. I was suggested by an user of some web forum to consult people here about my questions. Then I am here. I am a begginer of GNU/Linux. I've C100PA and have been searching about this laptop. I assume probably this uses coreboot, not u-boot. I am not sure yet even such things, though, I would like to make this laptop as secure as possible. The question is: firstly, I want to grasp whether C100PA has binary blob or not and how many proprietary software C100PA has in the initial state, or how. About the proprietary software, I am not sure if it is proper to ask here. So only if you are familiar with it, then if you can spare the time for me, they will help my understanding very much, really. Thank you very much for reading.

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can i install/compile coreboot at OrangePi RK3399
by sourcecode＠annopnod.com 10 Apr '19

10 Apr '19

can i install coreboot/compile at OrangePi RK3399. my project -install android and debian in Solid State Drive -boot using GNU GRUB? -boot from usb and install usb disk rufus source code and User manual for OrangePi RK3399=>http://www.orangepi.org/downloadresources/

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"Size of CBFS filesystem in ROM" parameter?
by Rafael Send 09 Apr '19

09 Apr '19

Hi, I'm trying to understand what the "Size of CBFS filesystem in ROM" setting actually does. If I make the size of the ROM chip large enough to contain my kernel & initrd (~15MB in this case) how do I need to modify this parameter? I've read up on the CBFS documentation, and while that provides good information on the CBFS layout & function, I was not able to connect the dots with the sizing parameter. Enlarging the value too much resulted in a failed build whereas enlarging it somewhat caused a working kernel to fail to load. If anyone could provide some pointers, they would be greatly appreciated! Cheers, R

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Shubhendra - GSoC proposal Inquiry about "Port payloads to RISC-V"
by Shubhendra Singhal 09 Apr '19

09 Apr '19

Dear Sir/Ma'am, I am Shubhendra Pal Singhal, currently third year in Computer Science at NIT Trichy, India. I wish to apply for Google Summer of Code. I looked into the profile of coreboot 4.9 and found out the project idea "*Port payloads to ARM, AArch64, MIPS or RISC-V*" to be very interesting. I have worked in the similar field on *RISCV architecture at IIT Madras where I helped in porting real time OS eChronos*, on RISCV architecture. I will be undergoing a *project in Embedded systems offered by USC Los Angeles in solving the SAT Solvers using OS and Digital Logic*. Furthermore, I am currently working on a *long term project with under Prof. N.Ramasubramanium on the AI chip* where we are trying to solve the processing speeds by efficiently reducing the number of writes in the cache for faster access. I am also *undergoing Microcontrollers and Microprocessors* as my core subject in my current semester and have already* undergone OS, Real time Systems* in my B.Tech IV semester. I have included my further details in my Linkedin : * <https://www.linkedin.com/in/shubhendra-singhal-7378a9131/>https://www.linkedin.com/in/ <https://www.linkedin.com/in/>shubhendra-singhal-7378a9131/* I want to contribute to the open source community in the field of Operating Systems and this can prove to be an excellent platform for gaining experience in field of systems. This opportunity can pave my career, towards applied research in the field of Systems. *While browsing through the link, I saw the mailing list assigned for the project. It would be very useful if you could guide me as to what is expected in the project proposal and how can I serve the open source community in the best possible way. *Any guidance would be very useful and I hope to receive a reply soon. Thanking you for your time and consideration. Regards Shubhendra Pal Singhal National Institute Of Technology, Trichy, India Phone number : +91 9787888015 Email-id : shubhendrapalsinghal(a)gmail.com Linkedin : <https://www.linkedin.com/in/shubhendra-singhal-7378a9131/> https://www.linkedin.com/in/shubhendra-singhal-7378a9131/

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coreboot April 2019