I contact you since I am doing the same development as you.
In my company we developed a board based on Leaf-hill CRB from Intel. I am in the process of making a clean image of the bios and I find the following problem to see if you can help me.
Complete all the process that you comment having the account the last files of this year:
FSP: Intel MR5 (566285)
IFWI image: "Intel-atome-e3900-soc-ifwi-224-41-release-package" (I think it is the last one available). Inside it has a ready-to-record image in 8Mb SPI.
Do you know why most of the documents have 8mb images when the CRB that I have and my mother has 16Mb?
The Flash description is extracted from the image that the CRB originally has with the tool "ifdtool.c".
it is right?
Well with these elements I configure coreboot using "menuconfig" as you mentioned in your post, at first I had an error compiling because I did not choose to use the BLOBS repo that it has in this version.
Is that configuration fine?
Finally, I managed to buid but at the end the following legend appears:
This image contains the following sections that can be manipulated with this tool:
'SI_DESC' (size 4096, offset 0)
'IFWI' (size 3141632, offset 4096)
'COREBOOT' (CBFS, size 12703744, offset 3147776)
'RECOVERY_MRC_CACHE' (size 65536, offset 15851520)
'RW_MRC_CACHE' (size 65536, offset 15917056)
'RW_VAR_MRC_CACHE' (size 4096, offset 15982592)
'BIOS_UNUSABLE' (size 262144, offset 15986688)
'DEVICE_EXTENSION' (size 520192, offset 16248832)
'UNUSED_HOLE' (size 4096, offset 16773120)
It is possible to perform either the write action or the CBFS add/remove actions on every section listed above.
To see the image's read-only sections as well, rerun with the -w option.
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs master header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 34116 none
cpu_microcode_blob.bin 0x8600 microcode 46080 none
fallback/ramstage 0x13a80 stage 76438 none
config 0x26580 raw 304 none
revision 0x26700 raw 673 none
fallback/postcar 0x26a00 stage 16680 none
fallback/dsdt.aml 0x2ab80 raw 5581 none
fallback/payload 0x2c1c0 simple elf 67427 none
payload_config 0x3c980 raw 1637 none
payload_revision 0x3d040 raw 235 none
(empty) 0x3d180 null 12420632 none
bootblock 0xc157c0 bootblock 32768 none
Built intel/leafhill (Leafhill)
Image written successfully to build/cbfs/fallback/ifwi.bin.tmp.
Image does not contain sub-partition OBBP(6).
Sub-partition IBBP(4) entry IBBL replaced from file build/cbfs/fallback/bootblock.bin.
Image written successfully to build/cbfs/fallback/ifwi.bin.tmp.
W: Written area will abut bottom of target region: any unused space will keep its current contents
** WARNING **
coreboot has been built without an Intel Firmware Descriptor.
Never write a complete coreboot.rom without an IFD to your
board's flash chip! You can use flashrom's IFD or layout
parameters to flash only to the BIOS region.
To you this warning happens, because of that the .bin is not generated to download in the SPI memory.
Can you help me with this situation?
Hello, this is my first post here.
I was suggested by an user of some web forum to consult people here about my questions. Then I am here. I am a begginer of GNU/Linux.
I've C100PA and have been searching about this laptop. I assume probably this uses coreboot, not u-boot. I am not sure yet even such things, though, I would like to make this laptop as secure as possible.
The question is: firstly, I want to grasp whether C100PA has binary blob or not and how many proprietary software C100PA has in the initial state, or how. About the proprietary software, I am not sure if it is proper to ask here.
So only if you are familiar with it, then if you can spare the time for me, they will help my understanding very much, really.
Thank you very much for reading.
can i install coreboot/compile at OrangePi RK3399.
-install android and debian in Solid State Drive
-boot using GNU GRUB?
-boot from usb and install usb disk rufus
source code and User manual for OrangePi RK3399=>http://www.orangepi.org/downloadresources/
I'm trying to understand what the "Size of CBFS filesystem in ROM" setting
If I make the size of the ROM chip large enough to contain my kernel &
initrd (~15MB in this case) how do I need to modify this parameter?
I've read up on the CBFS documentation, and while that provides good
information on the CBFS layout & function, I was not able to connect the
dots with the sizing parameter. Enlarging the value too much resulted in a
failed build whereas enlarging it somewhat caused a working kernel to fail
If anyone could provide some pointers, they would be greatly appreciated!
I am Shubhendra Pal Singhal, currently third year in Computer Science at
NIT Trichy, India. I wish to apply for Google Summer of Code. I looked into
the profile of coreboot 4.9 and found out the project idea "*Port payloads
to ARM, AArch64, MIPS or RISC-V*" to be very interesting.
I have worked in the similar field on *RISCV architecture at IIT Madras
where I helped in porting real time OS eChronos*, on RISCV architecture. I
will be undergoing a *project in Embedded systems offered by USC Los
Angeles in solving the SAT Solvers using OS and Digital Logic*.
Furthermore, I am currently working on a *long term project with under
Prof. N.Ramasubramanium on the AI chip* where we are trying to solve the
processing speeds by efficiently reducing the number of writes in the cache
for faster access. I am also *undergoing Microcontrollers and
Microprocessors* as my core subject in my current semester and have
OS, Real time Systems* in my B.Tech IV semester.
I have included my further details in my Linkedin : *
I want to contribute to the open source community in the field of Operating
Systems and this can prove to be an excellent platform for gaining
experience in field of systems. This opportunity can pave my career,
towards applied research in the field of Systems.
*While browsing through the link, I saw the mailing list assigned for the
project. It would be very useful if you could guide me as to what is
expected in the project proposal and how can I serve the open source
community in the best possible way. *Any guidance would be very useful and
I hope to receive a reply soon. Thanking you for your time and
Shubhendra Pal Singhal
National Institute Of Technology, Trichy, India
Phone number : +91 9787888015
Email-id : shubhendrapalsinghal(a)gmail.com
Linkedin : <https://www.linkedin.com/in/shubhendra-singhal-7378a9131/>
In order to add Nvidia Optimus support on Lenovo laptops, I'm trying to
fix the last issues on , but I need your help to do some test on
On Lenovo Sandy Bridge / Ivy Bridge series the PMH7 register 0x50
controls dGPU power.
Comments on Gerrit show that different bits on different generations are
Please use util/pmh7tool on vendor firmware with Optimus enabled and
graphics driver loaded:
$ ./pmh7tool -r 0x50
To wake the GPU from sleep, you can simply run lspci, or a graphical 3D
It will go back to sleep after a few seconds of idle.
Please report which bits toggle and the device you run tests on.
It will help to add proper Nvidia Optimus support to all Lenovo laptops.