coreboot February 2019

coreboot@coreboot.org

51 participants
43 discussions

Re: Caby lake support
by Zaolin 20 Feb '19

20 Feb '19

There are Intel reference boards. You can find them in the code under: src/mainboard/intel/ A Kaby Lake reference board should be kblrvp. On 20.02.19 11:29, Mayuri Tendulkar wrote: > > Thanks for quick response. > > > > I see below release- this support is added. > > > > https://coreboot.org/releases/coreboot-4.8.1-relnotes.txt > > > > Is there any reference board used with this chipset , which can be > referred as some POC? > > > > *From:*Angel Pons <th3fanbus(a)gmail.com> > *Sent:* 20 February 2019 15:55 > *To:* Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> > *Cc:* coreboot <coreboot(a)coreboot.org> > *Subject:* Re: [coreboot] Caby lake support > > > > ** This mail has been sent from an external source ** > > > > Hello, > > On Wed, Feb 20, 2019, 11:23 Mayuri Tendulkar > <mayuri.tendulkar(a)aricent.com <mailto:mayuri.tendulkar@aricent.com> wrote: > > Is there support for Intel Cabylake chipset in latest coreboot? > > Kaby Lake? Yes. > > ===================================================== > Please refer to http://www.aricent.com/email-disclaimer > for important disclosures regarding this electronic communication. > ===================================================== > > _______________________________________________ > coreboot mailing list -- coreboot(a)coreboot.org > To unsubscribe send an email to coreboot-leave(a)coreboot.org

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Re: Caby lake support
by Angel Pons 20 Feb '19

20 Feb '19

Hello, On Wed, Feb 20, 2019, 11:23 Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com wrote: > Is there support for Intel Cabylake chipset in latest coreboot? > Kaby Lake? Yes. >

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Caby lake support
by Mayuri Tendulkar 20 Feb '19

20 Feb '19

Hi Team Is there support for Intel Cabylake chipset in latest coreboot? [cid:image001.png@01D4C934.5B4BE590] Regards Mayuri ===================================================== Please refer to http://www.aricent.com/email-disclaimer for important disclosures regarding this electronic communication. =====================================================

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FSP Memory down setup
by Zvi Vered 17 Feb '19

17 Feb '19

Helllo, In my BayTrail module, Enable Memory Down = Enabled. In this case are the following parameters relevant ? DIMM 0 Enable DIMM 1 Enable DIMM_DWidth DIMM_Density DIMM _BusWidth DIMM_Sides Thank you, Zvika

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[x86] Support for SIS 651 (Northbridge) + SIS 962 (Southbridge) ?
by Frederic Dumas 15 Feb '19

15 Feb '19

Hi ! Thanks to a face to face talk at FOSDEM 2019 in Brussels, with Philippe, a German Coreboot speaker (and developer ? He knows better than me), I was said that dropping a mail to the list and asking for possible support of my desktop motherboard would not break your rules. So I do now. We are dealing here with legacy Pentium IV hardware (circa 2004, ugh!) Northbridge: SIS 651 http://www.cpu-upgrade.com/mb-SiS_(chipsets)/651.html iGPU: SIS 315 (w/ SIS 301B) (unused, PCI GPU GT430 in use) Southbridge: SIS 962 Processor: Pentium IV Northwood 3.06Ghz HT 512K L2 533MT/s FSB http://www.cpu-upgrade.com/CPUs/Intel/Pentium_4/RK80532PE083512.html I may provide more details, but I guess this is enough to check if I am facing a wall, or if most of the work has been already done at tuning Coreboot for firing up this kind of hardware. Thank you ! Frederic PS: I attached here below a lspci -v output. -- Frédéric Dumas f.dumas(a)ellis.siteparc.fr 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 651 Host (rev 02) Subsystem: ASUSTeK Computer Inc. Device 8081 Flags: bus master, medium devsel, latency 32 Memory at e5000000 (32-bit, non-prefetchable) [size=4M] Capabilities: [c0] AGP version 2.0 Kernel driver in use: agpgart-sis Kernel modules: sis_agp 00:01.0 PCI bridge: Silicon Integrated Systems [SiS] AGP Port (virtual PCI-to-PCI bridge) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 Kernel modules: shpchp 00:02.0 ISA bridge: Silicon Integrated Systems [SiS] SiS962 [MuTIOL Media IO] LPC Controller (rev 14) Flags: bus master, medium devsel, latency 0 00:02.1 SMBus: Silicon Integrated Systems [SiS] SiS961/2/3 SMBus controller Flags: medium devsel I/O ports at e600 [size=32] Kernel driver in use: sis96x_smbus Kernel modules: i2c_sis96x 00:02.5 IDE interface: Silicon Integrated Systems [SiS] 5513 IDE Controller (prog-if 80 [ISA Compatibility mode-only controller, supports bus mastering]) Subsystem: ASUSTeK Computer Inc. Device 807a Flags: bus master, medium devsel, latency 128, IRQ 16 [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] [virtual] Memory at 000003f0 (type 3, non-prefetchable) [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] [virtual] Memory at 00000370 (type 3, non-prefetchable) I/O ports at b400 [size=16] Kernel driver in use: pata_sis Kernel modules: pata_acpi 00:02.7 Multimedia audio controller: Silicon Integrated Systems [SiS] SiS7012 AC'97 Sound Controller (rev a0) Subsystem: ASUSTeK Computer Inc. Device 8095 Flags: bus master, medium devsel, latency 32, IRQ 18 I/O ports at a400 [size=256] I/O ports at a000 [size=128] Capabilities: [48] Power Management version 2 Kernel driver in use: snd_intel8x0 Kernel modules: snd_intel8x0 00:03.0 USB controller: Silicon Integrated Systems [SiS] USB 1.1 Controller (rev 0f) (prog-if 10 [OHCI]) Subsystem: ASUSTeK Computer Inc. Device 807a Flags: bus master, medium devsel, latency 32, IRQ 9 Memory at e4000000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci-pci 00:03.1 USB controller: Silicon Integrated Systems [SiS] USB 1.1 Controller (rev 0f) (prog-if 10 [OHCI]) Subsystem: ASUSTeK Computer Inc. Device 807a Flags: bus master, medium devsel, latency 32, IRQ 21 Memory at e3800000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci-pci 00:03.2 USB controller: Silicon Integrated Systems [SiS] USB 1.1 Controller (rev 0f) (prog-if 10 [OHCI]) Subsystem: ASUSTeK Computer Inc. Device 807a Flags: bus master, medium devsel, latency 32, IRQ 22 Memory at e3000000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci-pci 00:03.3 USB controller: Silicon Integrated Systems [SiS] USB 2.0 Controller (prog-if 20 [EHCI]) Subsystem: ASUSTeK Computer Inc. Device 807a Flags: bus master, medium devsel, latency 32, IRQ 23 Memory at e2800000 (32-bit, non-prefetchable) [size=4K] Capabilities: [50] Power Management version 2 Kernel driver in use: ehci-pci 00:0e.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) Flags: bus master, 66MHz, medium devsel, latency 32, IRQ 17 Bus: primary=00, secondary=02, subordinate=02, sec-latency=32 I/O behind bridge: 00009000-00009fff Memory behind bridge: e0800000-e27fffff Prefetchable memory behind bridge: e5f00000-f3efffff Capabilities: [40] Power Management version 2 Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [60] Express PCI/PCI-X to PCI-Express Bridge, MSI 00 Kernel modules: shpchp 00:0f.0 Ethernet controller: Broadcom Inc. and subsidiaries BCM4401 100Base-T (rev 01) Subsystem: ASUSTeK Computer Inc. A7V8X motherboard Flags: bus master, fast devsel, latency 32, IRQ 18 Memory at e0000000 (32-bit, non-prefetchable) [size=8K] Capabilities: [40] Power Management version 2 Kernel driver in use: b44 Kernel modules: b44 00:10.0 CardBus bridge: ENE Technology Inc CB-710/2/4 Cardbus Controller (rev 01) Subsystem: ENE Technology Inc CB-710/2/4 Cardbus Controller Flags: bus master, medium devsel, latency 168, IRQ 16 Memory at fe800000 (32-bit, non-prefetchable) [size=4K] Bus: primary=00, secondary=03, subordinate=06, sec-latency=176 Memory window 0: 80000000-83ffffff (prefetchable) Memory window 1: 84000000-87ffffff I/O window 0: 00001000-000010ff I/O window 1: 00001400-000014ff 16-bit legacy interface ports at 0001 Capabilities: [a0] Power Management version 1 Kernel driver in use: yenta_cardbus Kernel modules: yenta_socket 00:10.1 FLASH memory: ENE Technology Inc CB710 Memory Card Reader Controller Subsystem: ASUSTeK Computer Inc. Device 1724 Flags: medium devsel, IRQ 19 I/O ports at 8800 [size=128] Capabilities: [a0] Power Management version 2 Kernel driver in use: cb710 Kernel modules: cb710 00:13.0 Multimedia video controller: Conexant Systems, Inc. CX23880/1/2/3 PCI Video and Audio Decoder (rev 05) Subsystem: Hauppauge computer works Inc. WinTV HVR-4000-HD Flags: bus master, medium devsel, latency 32, IRQ 18 Memory at df000000 (32-bit, non-prefetchable) [size=16M] Capabilities: [44] Vital Product Data Capabilities: [4c] Power Management version 2 Kernel driver in use: cx8800 Kernel modules: cx8800 00:13.1 Multimedia controller: Conexant Systems, Inc. CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port] (rev 05) Subsystem: Hauppauge computer works Inc. WinTV HVR-4000-HD Flags: bus master, medium devsel, latency 32, IRQ 18 Memory at de000000 (32-bit, non-prefetchable) [size=16M] Capabilities: [4c] Power Management version 2 Kernel driver in use: cx88_audio Kernel modules: cx88_alsa 00:13.2 Multimedia controller: Conexant Systems, Inc. CX23880/1/2/3 PCI Video and Audio Decoder [MPEG Port] (rev 05) Subsystem: Hauppauge computer works Inc. WinTV HVR-4000-HD Flags: bus master, medium devsel, latency 32, IRQ 18 Memory at dd000000 (32-bit, non-prefetchable) [size=16M] Capabilities: [4c] Power Management version 2 Kernel driver in use: cx88-mpeg driver manager Kernel modules: cx8802 00:13.4 Multimedia controller: Conexant Systems, Inc. CX23880/1/2/3 PCI Video and Audio Decoder [IR Port] (rev 05) Subsystem: Hauppauge computer works Inc. WinTV HVR-4000-HD Flags: bus master, medium devsel, latency 32, IRQ 255 Memory at dc000000 (32-bit, non-prefetchable) [disabled] [size=16M] Capabilities: [4c] Power Management version 2 02:00.0 VGA compatible controller: NVIDIA Corporation GF108 [GeForce GT 430] (rev a1) (prog-if 00 [VGA controller]) Subsystem: ZOTAC International (MCO) Ltd. Device 2200 Flags: bus master, fast devsel, latency 0, IRQ 24 Memory at e1000000 (32-bit, non-prefetchable) [size=16M] Memory at e8000000 (64-bit, prefetchable) [size=128M] Memory at e6000000 (64-bit, prefetchable) [size=32M] I/O ports at 9800 [size=128] Expansion ROM at 000c0000 [disabled] [size=128K] Capabilities: [60] Power Management version 3 Capabilities: [68] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [78] Express Endpoint, MSI 00 Capabilities: [b4] Vendor Specific Information: Len=14 <?> Kernel driver in use: nouveau Kernel modules: nvidiafb, nouveau 02:00.1 Audio device: NVIDIA Corporation GF108 High Definition Audio Controller (rev a1) Subsystem: ZOTAC International (MCO) Ltd. Device 2200 Flags: bus master, fast devsel, latency 0, IRQ 18 Memory at e0800000 (32-bit, non-prefetchable) [size=16K] Capabilities: [60] Power Management version 3 Capabilities: [68] MSI: Enable- Count=1/1 Maskable- 64bit+ Capabilities: [78] Express Endpoint, MSI 00 Kernel driver in use: snd_hda_intel Kernel modules: snd_hda_intel

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Refactor tianocore payload
by Patrick Rudolph 15 Feb '19

15 Feb '19

Hi folks! With UEFI the defactor standard it seems reasonable to improve the tianocore payload integration. I'm having trouble to compile "stable" and "master" is totally broken as packages have been removed. Instead of the current approach of maintaining patches in our tree, I'd like to use a repo that has those patches applied and is known to be working. A good candiate is [1], as it's maintained, has bug-fixes and features upstream tianocore doesn't provide, and it's known to work with coreboot out of the box. Similar to seabios, we should use this repo without additional in-tree patches to build a working payload. Please tell me what you think about the proposed solution. [1]: https://github.com/MrChromebox/edk2 -- Patrick Rudolph 9elements Agency GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: patrick.rudolph(a)9elements.com Phone: +49 234 68 94 188 Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 17519 Geschäftsführung: Sebastian Deutsch, Daniel Hoelzgen

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Random System Freezes
by Kinky Nekoboi 14 Feb '19

14 Feb '19

Anybody having FUN with random system Freezes with coreboot 4.9? Experienced some in the Last days on. my X220 and F2a85m board both with Debian Buster/ +Cinnamon best regards

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hang in walkcbfs.S on skylake SP
by Jonathan Zhang 14 Feb '19

14 Feb '19

Hi, I am working on porting coreboot to Skylake SP and OCP Tiogapass with FSP 2.0. I have a strange issue that I hope to get some wisdom. The boot hangs when executing this line "sub %ecx, %ebx" in src/arch/x86/walkcbfs.S; the post code showing up is 0xb1. When I add a spinloop before this statement "sub %ecx, %ebx", the postcode stays at 0x21, which means code execution till this point is smooth. My codebase is based on current tip of upstream code. In the .config file, following are set (greping BOOTBLOCK): CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_BOOTBLOCK_CPU_INIT="soc/intel/fsp_skylake_fsp/bootblock/bootblock.c" CONFIG_ARCH_BOOTBLOCK_X86_32=y CONFIG_BOOTBLOCK_SIMPLE=y CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_C_ENVIRONMENT_BOOTBLOCK=y Any pointer is appreciated. Let me know if you need any additional information. Thank you, Jonathan

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cleaning crossgcc tools
by galla rao 13 Feb '19

13 Feb '19

Hi All, To pull cross compile tools in Coreboot the below command is run, make crossgcc-i386 CPUS=6 Is there a step or a command to clean all the tools that got installed ? Regards Ranga

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getting rid of CAR_GLOBAL and early_variables.h
by Arthur Heymans 13 Feb '19

13 Feb '19

Hi Currently most x86 platforms have CONFIG_NO_CAR_GLOBAL_MIGRATION set by implementing POSTCAR_STAGE. This means that global variables during CAR stages don't need to be migrated to cbmem when initializing cbmem, as stages are cleanly separated programs (in other words you don't tear down CAR while running code in CAR). Previously we had a CAR_GLOBAL macro that would put global variables a 'special' place in car. with NO_CAR_GLOBAL_MIGRATION this is not needed anymore. I propose to remove all those CAR_GLOBAL references on platforms already implementing POSTCAR_STAGE. see [1]. That way future platforms that tend to copy a lot of this code don't needlessly end up using this meaningless macro. Now moving forward it would be a nice goal to set for the October release 2020 to have NO_CAR_GLOBAL_MIGRATION as a mandatory feature? This was already discussed in [2], without a decisive conclusion. [1]https://review.coreboot.org/q/topic:%2522no_CAR_GLOBAL%2522+ [2]https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/V…

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coreboot February 2019