coreboot October 2019

coreboot@coreboot.org

67 participants
59 discussions

[RFC] Using relocatable module program parameters to pass cbmem_top() on X86
by Arthur Heymans 21 Oct '19

21 Oct '19

Hi Currently all stages that need cbmem need an implementation of a cbmem_top function. On platforms with fully open source coreboot code it is generally not a problem to link in all stages the code reading the hardware registers to figur out where the top of lower memory is. On FSP platforms this proves to be painful and using the value provided by the FSP-M HOB is to be preferred. Next stages don't have access to this variable since CAR is gone. EBDA is used to pass it on to next stages. The problem with this is that EBDA also need to be written on S3 as one cannot assume it to be still there. Writing things on S3 is always fragile as it could overwrite other things set up by something else. One possible solution is to back up the area it's going to write to in romstage in cbmem and restoring it on the ramstage, but writing to cbmem on S3 resume is just moving the problem to a different place and likely makes things even worse... One other idea I could come up with is to make the cbmem_top pointer an argument to the relocatable stages needing it (postcar and ramstage). This would unify all cbmem_top implementation in those stages and should be more robust on S3 resume as on S3 resume the ramstage is typically fetched from RAM (cbmem or tseg stage cache). Any thoughts? Arthur Heymans

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intel e2176m coreboot
by halilibrahim.ramazan＠bmc.com.tr 21 Oct '19

21 Oct '19

hi everyone, I'm a beginner of coreboot. I need to know where should i start. Actually i follow some steps mentioned here : "https://doc.coreboot.org/tutorial/part1.html". And i made it. after all a coreboot.rom file prepared according to my board that include intel xeon e 2176m and rom size 16MB and according to coffelake h. But i guess i made a mistake because it didn't work. But i don't know where exactly i fail or what is the missing part. Could you help me? Is there any manual document should i follow or steps or any other idea? Thanks.

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How to use crossgcc-i386 during make?
by Naveen Chaudhary 20 Oct '19

20 Oct '19

As per the Wiki : https://www.coreboot.org/Build_HOWTO I did "make crossgcc-i386". Now when I do make, I get compilation errors because my host gcc verion is 4.3. In case I update the host gcc version is updated to some later version, says gcc-8 , the errors are gone. Looks like coreboot build system still uses the host gcc. How can I make with coreboot toolchain, instead of the host gcc toolchain. Regards, Naveen Build HOWTO - coreboot<https://www.coreboot.org/Build_HOWTO> This page describes how you can build a coreboot image for your specific mainboard. www.coreboot.org

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Trouble jumping from bootblock to romstage
by Marty E. Plummer 20 Oct '19

20 Oct '19

Hello. So as you may be aware, I've taken on the immense task of porting coreboot to the ppc64/power9/talos ii platform. I've figured out how to get the sbe and hostboot bootloader to load and execute my bootblock, and figured out just enough of qemu and gdb to be able to make some bad debugging decisions, but I'm stuck somewhere in run_romstage, specifically in src/lib/cbfs.c:cbfs_master_header_props. I get so far as `size_t fmap_top` which appears to have a correct value (gdb says its 0x3fff000, and this is a 64mb flash chip. 0x3ffefc0-0x3fff000 in the rom has `LARCHIVE....<header pointer... BCZL` so that looks right, I think), then offset has the value 0x3ffeffc, which contains the bytes '0x381102fc' in the rom and then the second rdev_readat causes it to return -1, and I end up in hlt(). at this point, `print *&header` shows the struct to be mostly filled with 0xdeadbeef, with the exception of the offset, which says '0x9fda0'. This does not appear to be the address of anything in the rom as far as I can tell. I'm not certain what else I could do from this point. If any of you folks have suggestions or ideas, I would greatly appreciate an assist. For the record, the code is being written using the elfv2 abi, and is big endian, if that matters. Regards, Marty

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Trouble jumping from bootblock to romstage
by Marty E. Plummer 20 Oct '19

20 Oct '19

Hello. So as you may be aware, I've taken on the immense task of porting coreboot to the ppc64/power9/talos ii platform. I've figured out how to get the sbe and hostboot bootloader to load and execute my bootblock, and figured out just enough of qemu and gdb to be able to make some bad debugging decisions, but I'm stuck somewhere in run_romstage, specifically in src/lib/cbfs.c:cbfs_master_header_props. I get so far as `size_t fmap_top` which appears to have a correct value (gdb says its 0x3fff000, and this is a 64mb flash chip. 0x3ffefc0-0x3fff000 in the rom has `LARCHIVE....<header pointer... BCZL` so that looks right, I think), then offset has the value 0x3ffeffc, which is ARCHIVE of the above region, and then the second rdev_readat causes it to return -1, and I end up in hlt(). at this point, `print *&header` shows the struct to be mostly filled with 0xdeadbeef, with the exception of the offset, which says '0x9fda0'. This does not appear to be the address of anything in the rom as far as I can tell. I'm not certain what else I could do from this point. If any of you folks have suggestions or ideas, I would greatly appreciate an assist. For the record, the code is being written using the elfv2 abi, and is big endian, if that matters. Regards, Marty

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DIY debug Dongle
by alejandro.estay＠gmail.com 18 Oct '19

18 Oct '19

Hi I've seen an EHCI debug dongle in the old wiki. I'm trying to build one for 2 purposes: debug a homebrew os/Shell and make it a new UEFI bootloader. However I don't know where to find further documentation or comments about this. I also dont' know what is the current or most up to date schematic to build the "sandwich" and what tracks cut and what not. I have bought those blue cypress FX2LP boards and I don't know how to check revisions. Also, I'dont know exactly what software can be used to control it. It would be desirable if one can send stop or install some breakpoints with Visual studio's debugger or WinDBG or GDB or something like that. thanks in advance for your advice.

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Re: OpenBMC on KGPE-D16, somebody has it working?
by Insurgo 17 Oct '19

17 Oct '19

OpenBMC for the KGPE-D16 is here and "works": https://www.raptorengineering.com/coreboot/kgpe-d16-bmc-port-status.php This is stale, PoC state quality: - SSH password is hardcoded to 0penBMC - TTY gets corrupted after a while and OpenBMC needs to be restarted to fix the issue (asus_power.sh reset) - Thermal management is for server, not workstation. That needs to be hacked to not have all fans, full speed, all the time since AST2050 controls thermal management when powered up. - REST API is exposed If you want the OpenBMC bitbake binary produced, let me know. u-bmc would be awesome. I opened this ticket for u-bmc's KGPE-D16: https://github.com/u-root/u-bmc/issues/133 Regards, Thierry/Insurgo On 10/13/19 1:11 AM, ron minnich wrote: > If you like running systemd on your bmc, the minimum 60 seconds > openbmc takes to boot, the complex, fragile, and long time it takes to > build from source, and the openbmc stack's need for giant memory > footprint and lots of nvme, stop reading. > > IF, OTOH, you like the idea of a very lightweight stack, which builds > in minutes not hours, and needs maybe 32M of memory to run, and boots > much faster, well, you might want to checkout u-bmc. > > https://github.com/u-root/u-bmc > > On Sat, Oct 12, 2019 at 2:00 PM Kinky Nekoboi <kinky_nekoboi(a)nekoboi.moe> wrote: >> Debian 10. >> >> Thats perfect i have the nessary flashing tools. >> >> >> Am 12.10.19 um 22:57 schrieb Merlin Büge: >>> Hi, >>> >>>> Due to lib depenency hell i am not able to build openbmc myself atm. >>>> >>> Are you building on Debian (9 or 10)? >>> >>>> Does somebody has openbmc working for there kgpe-d16 system and can >>>> maybe send me a rom ? >>> I'll send you a separate email. >>> >>>> Can i flash the module with a Programmer and testclip or only internally? >>> Yes, a SOIC16 testclip and an SPI programmer like the CH341a will work. >>> >>> >>> Merlin >>> >>> >> _______________________________________________ >> coreboot mailing list -- coreboot(a)coreboot.org >> To unsubscribe send an email to coreboot-leave(a)coreboot.org > _______________________________________________ > coreboot mailing list -- coreboot(a)coreboot.org > To unsubscribe send an email to coreboot-leave(a)coreboot.org

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coreboot on new Supermicro boards with AMD Epyc CPUs?
by Christoph Zechner 17 Oct '19

17 Oct '19

Hi there, is anyone working on coreboot for new supermicro boards with AMD Epyc CPUs right now or is planning on doing this? I'd appreciate any information for future upgrade plans. :-) Thanks in advance! Best regards Christoph Zechner

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Ifdtool for modifying IFD 2.0?
by Rafael Send 17 Oct '19

17 Oct '19

Hi, I'm trying to make some adjustments to my descriptor. The -D switch results in an error which goes something like "Density modifications to IFD 2.0 not supported yet". Is there a version of the tool (or a different tool) which will let me make these changes? Note that I seem to be able to read / dump the contents just fine. Cheers, Rafael

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How to configure ECC memory through FSP 1.0 (Baytrail)
by Alexey Borovikov 17 Oct '19

17 Oct '19

I have is board on Soc Baytrail processor with ECC memory. After setting the correct memory parameters through the FSP, the board started. But when I try to set the “BakerSport Platform (ECC) Type” parameter, the board stops booting with post code 2a. There are no more parameters in FSP for ECC memory. What other options can I try? What am I doing wrong?

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coreboot October 2019