coreboot October 2019

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67 participants
59 discussions

Re: F2A85-M - amdgpu fails, integrated GPU works fine
by Mike Banon 12 Oct '19

12 Oct '19

Please could you share your coreboot boot log after applying this patch? Available with ./coreboot/util/cbmem utility On Fri, Oct 11, 2019 at 6:11 PM Grzegorz Bogdał <bogdal.grzegorz(a)tutanota.com> wrote: > > I've tried the patch from csb_patcher. I've applied only the lenovog505s_dgpu patch. Unfortunately, nothing changed. > > > Sep 14, 2019, 14:04 by mikebdp2(a)gmail.com: > > Kinky, have you tried a patch mentioned in my previous message? If > yes, what are the results? > > On Thu, Sep 12, 2019 at 2:31 PM Kinky Nekoboi <kinky_nekoboi(a)nekoboi.moe> wrote: > > > Also user of said board. > > For me only Nvidia GPUs work correctly. > > But using an older Version from 2018, because S3 works there. > > > Am 10.09.19 um 11:05 schrieb Mike Banon: > > Indeed, this patch -- https://review.coreboot.org/c/coreboot/+/31448 ( > > src/device/pci: Add support for discrete VGA initialization and OpROM > > loading ) -- could help, because it will create the ACPI VFCT table > > for discrete RX 570 GPU instead of doing this for integrated HD 8670D. > > You could install it conveniently and securely with the help of > > csb_patcher.sh script ( > > http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#NEWS or > > https://review.coreboot.org/c/coreboot/+/33509 ). > > > > Although there will not be a VFCT for your integrated GPU, it should > > be working fine even without it, maybe at cost of a slightly higher > > power consumption. We have discovered that > > > > " ACPI VFCT - it's a table where AMD stores the Radeon video BIOS when > > the system is booted up in UEFI mode." > > " Where the ACPI VFCT Table is missing, Power States may not work properly. " > > > > so it seems without VFCT the integrated GPU is going to be at its' max > > TDP even while not loaded. For example, knowing that a total TDP of > > our G505S laptop's A10-5750M APU (CPU+GPU) does not exceed 35W and > > looking at the values for similar APUs at this table > > https://www.eteknix.com/amd-kaveri-a10-7850k-overclocking-analysis/7/ > > (all values except Intel / RAM / OC), approximately for our A10-5750M > > it should be > > > > Idle | GPU load | CPU+GPU load > > 15.6W | 23.66W | 35W > > 44.5% | 67.6% | 100% > > > > We already knew that A10-5750M is 15W at idle, but have learned that > > GPU adds approximately 23.66W - 15.6W = about 8W while at its' max > > TDP. This G505S laptop comes with a 65W PSU, so with iGPU at it max > > TDP -- the laptop's battery life will be smaller in about 65/(65-8) = > > 1.12 times. However I've never compared the consumption difference of > > coreboot vs UEFI, would be nice if someone could test it in practice. > > > > Since this RX 570 discrete PCI-E card should have its' own flash chip > > for storing the AtomBIOS blob -- unlike our laptop's onboard discrete > > HD-8570M or R5-M230 -- I think in your case there should not be a need > > of storing the discrete GPU's AtomBIOS ROM at your coreboot BIOS in > > addition to the integrated one. However, if the advice above would not > > work, you could try extracting the discrete GPU's AtomBIOS , using > > either https://www.coreboot.org/VGA_support#How_to_retrieve_a_good_video_bios > > or https://github.com/g505s-opensource-researcher/g505s-atombios#description > > | https://mail.coreboot.org/pipermail/coreboot/2017-July/084660.html > > instruction. > > > > Best regards, > > Mike > > > > On Mon, Sep 9, 2019 at 10:04 PM awokd via coreboot > > <coreboot(a)coreboot.org> wrote: > >> Grzegorz Bogdał: > >>> Thank you. I'll check it out and report sometime in September whether the patches helped my case. > >> Please note, AFAIK they have only been tested on G505s's, so may need > >> some modification for your platform. > >> > >> _______________________________________________ > >> coreboot mailing list -- coreboot(a)coreboot.org > >> To unsubscribe send an email to coreboot-leave(a)coreboot.org > > _______________________________________________ > > coreboot mailing list -- coreboot(a)coreboot.org > > To unsubscribe send an email to coreboot-leave(a)coreboot.org > >

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Basic hardware documentation
by Christoph Pomaska 11 Oct '19

11 Oct '19

Hi, I had the idea of contributing basic information about hardware components to the coreboot documentation in the style of "What is Super I/O?" and similar. What do other people think of that? Best regards Christoph Pomaska hosting.de GmbH Franzstr. 51 52064 Aachen Telefon: 0241 46314 480 Telefax: 0241 46314 489 http://www.hosting.de Registergericht: Amtsgericht Aachen Registernummer: HRB 13988 Geschäftsführer: Oliver Dick, Oguzhan Gökal

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Lenovo G505s to give for working on it
by Denis 'GNUtoo' Carikli 11 Oct '19

11 Oct '19

Hi, I was given a Lenovo G505s, but I would probably not have time to work on finishing to replace the nonfree software that is still needed for it. I was also given the opportunity to ship it to people interested in working on it. I've not looked into which exact hardware configuration it has, however as I understand, beside keeping it working in Coreboot, there are still some nonfree software that needs to be replaced: - There is a nonfree SMU firmware shipped as part of AGESA. - There is one or two ATI GPU which requires the following nonfree software: - The ATOM BIOS tables: this is bytecode that is required by the Linux Radeon driver to initialize the GPU. That is part of the video option rom. - The video option rom. - The various nonfree firmware for the Radeon GPU. - I'm unsure about the status without the nonfree CPU microcode. - There was also some work to replace the nonfree code that runs on the embedded controller, but I don't know the status. The laptop is currently situated in the USA, and I come back to France on Sunday so there is unfortunately very few time for me to decide if it needs to be shipped from the USA or from France. Denis.

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Adding System76 to End Users webpage
by Jeremy Soller 10 Oct '19

10 Oct '19

Hello, Now that System76 is providing products with Coreboot pre-installed, is it possible to add us to Consumer platforms on https://www.coreboot.org/users.html ? Also, we have a distribution of firmware utilizing Coreboot, EDK2, and open-source System76 firmware applications called System76 Open Firmware. Could this be added to Community/Custom coreboot images on that same page? Here is the link: https://github.com/system76/firmware-open Thanks! -- Jeremy Soller System76 Principal Engineer jeremy(a)system76.com

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SATA link 1 is not enabled
by Jorge Fernandez Monteagudo 09 Oct '19

09 Oct '19

Hi all, I'm trying to enable the SATA port 1 in an AMD bettong board. I've been able to enable port 0 adding in BiosCallOuts.c the next code after find it in other mainboard. AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) { ... /* sata configuration */ FchParams_reset->FchReset.SataEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2); ... } Once the system boots I see the kernel detects both SATA but the port 1 remains down although one disk is connected [ 0.715359] ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl SATA mode ... [ 0.716031] ata1: SATA max UDMA/133 abar m1024@0xf0b8d000 port 0xf0b8d100 irq 26 [ 0.716033] ata2: SATA max UDMA/133 abar m1024@0xf0b8d000 port 0xf0b8d180 irq 26 Anybody knows how to enable the SATA port 1? Regards Jorge

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Microcode update in coreboot on Intel HT enabled CPUs
by Patrick Rudolph 08 Oct '19

08 Oct '19

Dear microcode experts, please give us some feedback on how to do microcode updates properly in coreboot. While fixing a crash initializing Intel SGX on HT enabled CPUs I noticed that coreboot doesn't care for HT at all when doing MSR initialisation. I proposed the following patch [1], but it turns out that there are different opinions about updating microcode in parallel. In total there are four ways and only one can be correct: 1. Up to now coreboot updated all threads in parallel without a lock. That seems to follow Intel SDM (Order Number: 253668-070US) Chapter 8.7.11 2. According to Intel SDM (Order Number: 253668-070US) Chapter 9.11.6.3 microcode updates must only be done on one thread for each core, as long as the sibling thread doesn't do an update at time. 3. The kernel patch [2] states that the sibling thread must be idle while updating microcode on one core. 4. The "Bios Writers Guide" (Document Number 504790 / 550049) states that microcode must be done on all threads, but synchronized between sibling threads to only update one at a time. Which one is the correct way and how do you know? @Intel Can you update the SDM to clarify? Thank you for your time. 1: https://review.coreboot.org/c/coreboot/+/35739/ 2: https://lore.kernel.org/patchwork/patch/889353/ Regards, Patrick Rudolph 9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: patrick.rudolph(a)9elements.com Phone: +49 234 / 68 94 188 Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 13207 Geschäftsführung: Eray Basar, Sebastian Deutsch

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Question about booting windows10
by Yusuke Takano 08 Oct '19

08 Oct '19

To whom it may concern, I would like to enquire about the OS supported by coreboot. We are trying to boot Windows10 using coreboot. We were able to boot Windows10 Version 1607. However, we can't boot Windows10 Version 1809. Does coreboot support Windows10 Version 1809? I am sorry to trouble you, but please reply. Best Regards, Takano $B!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!](B $B%(%k%a%C%/%9-j!!@gBf;v6H=j(B $B!!!!!!!!!!9bLn!!M42p(B $B")(B981-0932 $B@gBf;T@DMU6hLZD.(B16-30$B!!%7%s%(%$LZD.%S%k(B2F Tel$B!!(B022-234-5270$B!!(BFax$B!!(B022-272-3673 E-mail: <mailto:h.eguchi@elmex-jp.com> y.takano(a)elmex-jp.com $B!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!]!](B

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G505S (coreboot AMD no-PSP laptop) being sold for a good price, 40 mins left
by Ivan Ivanov 08 Oct '19

08 Oct '19

Mike found a good condition G505S with top A10-5750M CPU preinstalled, being sold for a good price: https://www.ebay.com/itm/LENOVO-G505S-LAPTOP-WINDOWS-10-AMD-A10-WEBCAM-4GB-… Initially we wanted to share this link with our friend, but sadly he is not online in the moment and unlikely to come in time, so now sharing with everyone! Hopefully it could end up in the hands of a fellow coreboot'er. Please tell others if you'd like to bid, to avoid a bidding war between each other ;-)

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coreboot not working on Supermicro X11SSH-CTF
by Christoph Zechner 08 Oct '19

08 Oct '19

Hi there, we've been trying to get coreboot running on our X11SSH-CTF for days now and it is not working. Building the rom with board defaults (+ descriptor.bin) does not result in a bootable rom and shows the following errors: coreboot-4.10-807-g3356305ca6 Mon Sep 30 05:11:06 UTC 2019 bootblock starting (log level: 7)... CPU: Intel(R) Xeon(R) CPU E3-1220 v6 @ 3.00GHz CPU: ID 906e9, Kabylake H B0, ucode: 000000b3 CPU: AES supported, TXT supported, VT supported MCH: device id 5918 (rev 05) is Kabylake DT 2 PCH: device id a149 (rev 31) is Skylake PCH-H C236 IGD: device id ffff (rev ff) is Unknown CBFS: 'Master Header Locator' located CBFS at [cd3000:1000000) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 9d4c coreboot-4.10-807-g3356305ca6 Mon Sep 30 05:11:06 UTC 2019 romstage starting (log level: 7)... pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 TCO_STS: 0000 0001 GEN_PMCON: a0050200 00004006 GBLRST_CAUSE: 00010000 00000000 prev_sleep_state 5 CBFS: 'Master Header Locator' located CBFS at [cd3000:1000000) CBFS: Locating 'fspm.bin' CBFS: 'fspm.bin' not found. Could not locate fspm.bin in CBFS FSPM not available! Afterwards we built coreboot with the option "Add Intel FSP 2.0 binaries to CBFS", which resulted in: coreboot-4.10-807-g3356305ca6 Mon Sep 30 05:11:06 UTC 2019 bootblock starting (log level: 7)... CPU: Intel(R) Xeon(R) CPU E3-1220 v6 @ 3.00GHz CPU: ID 906e9, Kabylake H B0, ucode: 000000b3 CPU: AES supported, TXT supported, VT supported MCH: device id 5918 (rev 05) is Kabylake DT 2 PCH: device id a149 (rev 31) is Skylake PCH-H C236 IGD: device id ffff (rev ff) is Unknown CBFS: 'Master Header Locator' located CBFS at [cd3000:1000000) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size ad4c coreboot-4.10-807-g3356305ca6 Mon Sep 30 05:11:06 UTC 2019 romstage starting (log level: 7)... pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 TCO_STS: 0000 0001 GEN_PMCON: a0050200 00004006 GBLRST_CAUSE: 00010000 00000000 prev_sleep_state 5 CBFS: 'Master Header Locator' located CBFS at [cd3000:1000000) CBFS: Locating 'fspm.bin' CBFS: Found @ offset 55fc0 size 63000 POST: 0x34 FMAP: Found "FLASH" version 1.1 at be3000. FMAP: base = 0 size = 1000000 #areas = 26 FMAP: area RW_MRC_CACHE found @ b8d000 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' No memory dimm at address A0 No memory dimm at address A4 POST: 0x36 fef03848: 4b 42 4c 55 50 44 5f 4d 00 00 00 00 00 00 00 00 KBLUPD_M........ fef03858: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ fef03868: 01 00 00 00 00 00 00 00 00 80 f1 fe 00 80 02 00 ................ fef03878: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 . .............. fef03888: 00 00 44 00 00 00 00 00 c0 4e f0 fe c0 50 f0 fe ..D......N...P.. fef03898: c0 52 f0 fe c0 54 f0 fe 00 02 0f f0 00 f0 0f f0 .R...T.......... fef038a8: 0f 00 ff 00 ff 00 0f f0 00 f0 0f f0 0f 00 ff 00 ................ fef038b8: ff 00 02 00 01 03 06 04 07 05 01 03 02 00 05 07 ................ fef038c8: 06 04 c8 00 51 00 a2 00 64 00 28 00 28 00 17 00 ....Q...d.(.(... fef038d8: 28 00 01 00 00 01 00 00 00 00 40 00 00 00 80 00 (.........@..... fef038e8: 00 08 00 00 00 01 00 00 00 00 00 00 00 00 00 00 ................ fef038f8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... fef03928: 00 00 00 00 00 01 00 00 00 00 07 00 00 00 00 00 ................ fef03938: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... fef039b8: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 ................ fef039c8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 02 ................ fef039d8: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ fef039e8: 00 a0 d1 fe 00 b0 d1 fe 00 c0 d1 fe 01 00 00 00 ................ fef039f8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... fef03a68: 2c 01 64 00 00 00 01 01 01 00 00 00 00 00 00 00 ,.d............. fef03a78: 01 01 01 00 00 04 04 04 04 07 07 07 07 02 02 02 ................ fef03a88: 02 03 03 01 0c 0c 0c 0c 0c 0c 0c 0c 00 00 00 00 ................ fef03a98: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ fef03aa8: 00 00 00 00 00 00 00 df 03 00 00 00 00 00 00 00 ................ fef03ab8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... fef03b18: 00 00 00 01 01 00 01 00 00 00 01 00 00 00 00 00 ................ fef03b28: 00 00 00 01 00 00 00 00 00 00 00 08 00 00 00 00 ................ fef03b38: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ fef03b48: 00 00 01 00 00 00 00 00 00 00 01 01 00 00 d0 fe ................ fef03b58: fa 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ fef03b68: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... fef03d38: 00 00 00 01 00 18 00 00 a0 ef 00 00 00 00 00 00 ................ fef03d48: 00 00 00 00 00 00 00 00 15 01 00 00 12 02 00 ff ................ fef03d58: 01 00 07 03 00 00 00 00 00 00 00 00 00 00 00 00 ................ fef03d68: 54 45 53 54 01 00 01 01 01 01 00 02 00 02 02 02 TEST............ fef03d78: 00 00 00 01 00 02 02 00 00 00 00 00 00 00 00 00 ................ fef03d88: 00 00 00 01 07 07 07 07 07 07 07 07 07 07 07 07 ................ fef03d98: 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 ................ fef03da8: 07 07 07 07 02 02 02 02 02 02 02 02 02 02 02 02 ................ fef03db8: 02 02 02 02 b8 0b 02 00 10 27 02 00 00 00 00 00 .........'...... fef03dc8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... fef03de8: 00 00 00 20 00 01 00 00 01 01 00 01 00 01 00 00 ... ............ fef03df8: 01 00 01 01 00 00 00 00 00 00 00 00 00 00 00 00 ................ fef03e08: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... fef03e88: 00 00 00 00 00 00 aa 55 .......U POST: 0x92 Next step was taking the amberlake (kabylake was not working) fps files from the Intel repo [1] and using those to build coreboot with it (added option "Use the IntelFSP based binaries" and their paths) Any help would be much appreciated, thank you in advance! Best regards Christoph Zechner [1] https://github.com/IntelFsp/FSP/tree/master/AmberLakeFspBinPkg

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Linux kernel drivers to expose additional coreboot functions
by Patrick Rudolph 08 Oct '19

08 Oct '19

Dear folks, in order to better support userspace tools like fwupd[1] I've send patches to expose more coreboot functions using the google firmware drivers[2]. Both functions depend on the FMAP being placed in a cbmem buffer[3]. This particular patch set allows to read the FMAP and get the active CBFS partition in use. Please test and review. [1]: https://github.com/fwupd/fwupd/pull/1370 [2]: https://lkml.org/lkml/2019/10/8/378 [3]: https://review.coreboot.org/c/coreboot/+/35377 Regards, Patrick Rudolph 9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: patrick.rudolph(a)9elements.com Phone: +49 234 / 68 94 188 Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 13207 Geschäftsführung: Eray Basar, Sebastian Deutsch

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coreboot October 2019