coreboot June 2018

coreboot@coreboot.org

40 participants
105 discussions

OSFC 2018
by Zaolin 05 Jun '18

05 Jun '18

Dear Ladies and Gentlemen, We invite you to the Open Source Firmware Conference 2018 ( www.osfc.io ) which takes place at the 12th - 15th September in Erlangen, Germany. The OSFC 2018 is the first conference focusing exclusively on Open Source firmware. Therefore, our mission is to provide an appropriate platform to bring together as many Open Source projects, hardware manufacturers and developers as possible. In order to collaborate, share knowledge and push the Open Source firmware development. Get in touch with community of coreboot, LinuxBoot, Tianocore, u-boot and be part of our amazing firmware conference! Tickets are available: https://osfc.io/tickets CFP is available: https://easychair.org/cfp/osfc2018 Follow us on Twitter: osfc_io Best Regards, Philipp

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Reproducible builds
by Tom Hiller 05 Jun '18

05 Jun '18

Hi, I am trying to make a series of scripts with configs to help simplify the Coreboot build process for the Lenovo X230, and soon the X220, using the Coreboot-sdk Docker image. The one issue I am having is creating consistent builds. This was confusing after heading the news that Coreboot was reproducible and finding that the x230 was one of the many models confirmed here: https://tests.reproducible-builds.org/coreboot/coreboot.html. After doing some digging through the Coreboot git repo and searching gerrit, I found the config used, https://github.com/coreboot/coreboot/blob/master/configs/builder/config.len…, does not include payloads and that the IFD, ME and GBE binaries were sourced from "./site-local/" but I cannot find these files in any public repo. If these are not available, then the generated hashes cannot be confirmed outside of the reproducible-builds Jenkins environments. My question ultimately comes down to how much of Coreboot is reproducible and can a complete binary with payloads be built consistently given the same build enviroment? The more specific question is, if the downloading the Coreboot 4.8.1 release using this config, https://github.com/Thrilleratplay/coreboot-builder-scripts/blob/master/x230…, why would the SHA256 hashes never match and, at times, cbfstool partition sizes vary?

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KGPE-D16: Trouble using three PCIe cards simultaneously
by Daniel Kulesz 03 Jun '18

03 Jun '18

Hi folks, maybe this is not really coreboot-related, but I am experiencing an issue with the KGPE-D16 that there seems to be no working constellation how the following three cards can be put into service: - nvidia GPU (PCIe 3 x16, takes 1 slot but occupies two) - ASUS hypercard (PCIe 3 x16, takes 1 slot, has four M.2 slot with PCIe x4 each), see [1] - USB3 controller card (PCIe x4, takes 1 slot) No matter what I try, the hypercard is unable to detect more than two M.2 ssds. And only in the following config: 1 (MIO): empty 2: GPU 3: (GPU) 4: Hypercard 5: empty When I put the USB3 card in 5, only one of the M.2 ssds on the hypercard is recognized. Therefore, I also tried swapping stuff in many combinations such as the following: 1: empty 2: Hypercard 3: empty 4: USB3 5: GPU But no matter what I do, there seems to be now way to get all three cards working simulaneously. Even with JUST the hypercard and nothing else it will only detect two of the three M.2 cards inserted. :/ Seems like the vendor bios has the same issue. My plan now is to get a GPU that occupies only 1 slot and put the USB3 card next to it. Any help and clarifying explanations on this topic are warmly welcome. Cheers, Daniel [1] https://www.asus.com/Motherboard-Accessory/HYPER-M-2-X16-CARD/

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Re: [coreboot] KGPE-D16: Trouble using three PCIe cards simultaneously
by Jason Lenz 03 Jun '18

03 Jun '18

Hi Daniel, I also have a coreboot KGPE-D16 but am using different accessory cards. I took a look at the specs on your Hyper card and compared it to KGPE specs and I think one or more of the following might be the issue: * It looks like the Hyper card is a PCIE 3.0 device and the KGPE-D16 has PCIE 2.0 slots. * The Hyper card uses Intel VROC technology and I don't see that AMD cpus have an equivalent/compatible technology.

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 01 Jun '18

01 Jun '18

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. 19 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1391422: Incorrect expression (CONSTANT_EXPRESSION_RESULT) /src/soc/intel/broadwell/romstage/raminit.c: 128 in raminit() ________________________________________________________________________________________________________ *** CID 1391422: Incorrect expression (CONSTANT_EXPRESSION_RESULT) /src/soc/intel/broadwell/romstage/raminit.c: 128 in raminit() 122 123 printk(BIOS_DEBUG, "create cbmem for dimm information\n"); 124 mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); 125 memset(mem_info, 0, sizeof(*mem_info)); 126 /* Translate pei_memory_info struct data into memory_info struct */ 127 mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt; >>> CID 1391422: Incorrect expression (CONSTANT_EXPRESSION_RESULT) >>> "8 < 8" is always false regardless of the values of its operands because those operands are identical. This occurs as the logical first operand of "?:". 128 for (int i = 0; i < MIN(DIMM_INFO_TOTAL, PEI_DIMM_INFO_TOTAL); i++) { 129 struct dimm_info *dimm = &mem_info->dimm[i]; 130 const struct pei_dimm_info *pei_dimm = 131 &pei_data->meminfo.dimm[i]; 132 dimm->dimm_size = pei_dimm->dimm_size; 133 dimm->ddr_type = pei_dimm->ddr_type; ** CID 1271711: Control flow issues (DEADCODE) /src/include/device/hypertransport_def.h: 26 in offset_unit_id() ________________________________________________________________________________________________________ *** CID 1271711: Control flow issues (DEADCODE) /src/include/device/hypertransport_def.h: 26 in offset_unit_id() 20 21 22 static inline bool offset_unit_id(bool is_sb_ht_chain) 23 { 24 bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) 25 || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); >>> CID 1271711: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "1" inside this statement: "return need_offset && (1 ||...". 26 return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY 27 || is_sb_ht_chain); 28 } 29 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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coreboot June 2018