coreboot February 2017

coreboot@coreboot.org

66 participants
212 discussions

Re: [coreboot] Understand vboot logic to select FW_B
by tturne＠codeaurora.org 21 Feb '17

21 Feb '17

On 2017-02-15 13:34, Aaron Durbin wrote: > On Wed, Feb 15, 2017 at 3:20 PM, <tturne(a)codeaurora.org> wrote: >> On 2017-02-15 09:45, Aaron Durbin via coreboot wrote: >>> >>> On Wed, Feb 15, 2017 at 11:38 AM, <tturne(a)codeaurora.org> wrote: >>>> >>>> On 2017-02-15 07:46, Aaron Durbin via coreboot wrote: >>>>> >>>>> >>>>> On Tue, Feb 14, 2017 at 8:26 PM, <tturne(a)codeaurora.org> wrote: >>>>>> >>>>>> >>>>>> >>>>>> Folks, >>>>>> I'm working on coreboot on ARMv8 architecture and recently >>>>>> attempted to >>>>>> verify FW_B can be selected if FW_A is corrupted. >>>>>> >>>>>> In reviewing the code-path through coreboot vboot wrapper and >>>>>> vboot_reference library I'm not understanding the logic. >>>>>> >>>>>> The logic appears to be that vboot_reference library determines >>>>>> FW_A is >>>>>> corrupt and forces a reboot. >>>>>> >>>>>> After reboot, early in verstage_main(), both the NVRAM (flash) and >>>>>> vb2_context structures are initialized, wiping out any history of >>>>>> failure >>>>>> condition. >>>>>> >>>>>> I know I must be missing something in my analysis but don't see >>>>>> it. >>>>>> >>>>>> Can anybody on this list share their experiences in confirming the >>>>>> FW_B >>>>>> boot >>>>>> path if FW_A is corrupt? >>>>> >>>>> >>>>> >>>>> >>>>> ctx->flags & VB2_CONTEXT_FW_SLOT_B determines which slot to use. >>>>> The >>>>> vbnv (vboot non-volatile) storage keeps counts for slots to try. >>>>> vb2_select_fw_slot() will do that work for you. It's located in >>>>> firmware/2lib/2misc.c. That function is called from >>>>> vb2api_fw_phase2() >>>>> in firmware/2lib/2api.c. All this logic lives in vboot_reference >>>>> code >>>>> repository. >>>>> >>>> >>>> Thanks for this recap, I had identified most of this path >>>> previously. >>>> >>>> I can clearly see the corrupted A slot being detected and the status >>>> updated >>>> and vboot requesting a reboot. >>>> The reboot causes verstage to go through its initialization >>>> sequence, >>>> which >>>> in my case blows away the history of the reboot, so the cycle >>>> repeats >>>> endlessly. >>>> FW_A slot detected as corrupt reboot requested to boot from FW_B, >>>> reboot >>>> blows away this data and FW_A is detected to be corrupt and reboot >>>> requested, etc. >>>> >>>> I have verstage configured to run from bootblock, no DRAM/CBMEM >>>> available, >>>> just the RW_NVRAM fmap partition on the flash. >>>> I haven't made any change in vboot_reference or the coreboot vboot >>>> wrapper >>>> layer so for me, out of the box, something is amiss. >>> >>> >>> >>> The try count should drop on each reset. And then it should swap to >>> slot B. All of our ARMv8 and x86 boards utilize the same path. Have >>> you ensured your vbnv bindings are working? And dumping the vbnv >>> contents to the terminal each time might be helpful. I'm not sure >>> what >>> platform you are running so it's hard to know what configuration and >>> support files you are including. Do you have serial console logging >>> enabled? What's it say? >>> >>> If you don't have one of these set then you wouldn't be reading any >>> vbnv -- or saving: >>> >>> CONFIG_VBOOT_VBNV_CMOS >>> CONFIG_VBOOT_VBNV_EC >>> CONFIG_VBOOT_VBNV_FLASH >>> >>> Check out read_vbnv() and save_vbnv() in src/vboot/vbnv.c. >> >> >> CONFIG_VBOOT_VBNV_FLASH is set in our system. >> I think the key point I was missing before is the vboot reset has to >> retain >> vboot bss data. >> The vbnv_flash variable (static struct vbnv_flash_ctx) has to remain >> initialized across the reboot. > > No. We aren't reliant on that. It would get wiped on program load. If > it doesn't that's a bug. The vbnv is supposed to maintain the state > and the flow will reload the necessary state. > Aaron, thanks for your patience with me here. Putting printk statements in init_vbnv(), read_vbnv_flash() and save_vbnv_flash() clearly shows the NVRAM section is not being updated. This is first real test of spi-write functionality so this is likely culprit. Our unit-test does a page write that appeared to pass, so we are now looking closely at the spi-nor driver. Cheers, T.mike >> >> >>> >>>> >>>> I would be interested in hearing from anybody on the list on an >>>> ARMv8 >>>> target >>>> who has run the same test I'm trying to reproduce here. >>>> Specifically, I'm not running the test code in vboot_reference, I am >>>> manually corrupting partition A before flashing it. >>>> Cheers, >>>> T.mike >>>> >>>> >>>>> >>>>>> Cheers, >>>>>> T.mike >>>>>> >>>>>> -- >>>>>> coreboot mailing list: coreboot(a)coreboot.org >>>>>> https://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Is Xeon E5 supported?
by Taiidan＠gmx.com 20 Feb '17

20 Feb '17

On 02/19/2017 07:24 AM, Zheng Bao wrote: > Hi, All, > > We are evaluating a resolution, which requires more than four x8 PCIE lane. > > We assume Intel Xeon E5 can meet this requirement. > > > I am not quite familar with Intel platform. I am wondering if coreboot supports Xeon E5. > > Thanks. > > > Zheng What exactly do you want this for? x8 doesn't mean much without the pci-e version you want (1.0 x16 = 3.0 x4) You would have more flexibility platform wise if you used a pci-e expansion system like the ones from cyclone.com to add more pci-e slots.

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ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 20 Feb '17

20 Feb '17

The ASUS KGPE-D16 fails verification for branch master as of commit 5360c7ef94c9415fd0decd99b6a2d243f9c52e4c The following tests failed: BOOT_FAILURE Commits since last successful test: 5360c7e drivers/i2c: Use I2C HID driver for wacom devices See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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Re: [coreboot] install help
by qma ster 20 Feb '17

20 Feb '17

Hi Chris, you could read this article, it describes the laptop BIOS flashing procedure in a great detail: http://dangerousprototypes.com/docs/Flashing_a_BIOS_chip_with_Bus_Pirate Although it is written with Bus Pirate programmer in mind, other programmers like cheap CH341A have almost the same flashing instructions, just a flashrom command is slightly different! It would be much better if you learn how to do it by yourself, instead of relying on others to reflash your BIOS each time you need to install/update it. "give a man a fish and you feed him for a day; teach a man to fish and you feed him for a lifetime" 2017-02-20 14:23 GMT+03:00 njolk via coreboot <coreboot(a)coreboot.org>: > Dear coreboot community, > > I need help installing libreboot on my laptop, as I'm inexperienced with > the practices involved, and wish to avoid borking my device. might anyone > in Berlin be available to walk me through it? > > thank you so much in advance, > regards, > Chris Penn > > > > Sent with ProtonMail <https://protonmail.com> Secure Email. > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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install help
by njolk 20 Feb '17

20 Feb '17

Dear coreboot community, I need help installing libreboot on my laptop, as I'm inexperienced with the practices involved, and wish to avoid borking my device. might anyone in Berlin be available to walk me through it? thank you so much in advance, regards, Chris Penn Sent with [ProtonMail](https://protonmail.com) Secure Email.

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Re: [coreboot] Is Xeon E5 supported?
by Nico Huber 19 Feb '17

19 Feb '17

Hi Zheng, On 19.02.2017 13:24, Zheng Bao wrote: > Hi, All, > > We are evaluating a resolution, which requires more than four x8 PCIE lane. > > We assume Intel Xeon E5 can meet this requirement. > > > I am not quite familar with Intel platform. I am wondering if coreboot supports Xeon E5. short version: No. For current Intel platforms you need support in two places: The silicon initialization blob (FSP) and some more support code in coreboot. For the latter part the question can easily be answered with no. For FSP (which you'd need anyway) it's hard to find an answer for higher-end products. Even if you only ask about support for desktop processors, the answers vary from yes (verbal) to no answer / relaying the question (in written form). The list of supported platforms in the FSP release notes is usually useless. I don't know how much work on the coreboot part would need to be done. But if you want to evaluate that, ask Intel first, if your targeted platform is / will be supported by FSP. Nico

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Is Xeon E5 supported?
by Zheng Bao 19 Feb '17

19 Feb '17

Hi, All, We are evaluating a resolution, which requires more than four x8 PCIE lane. We assume Intel Xeon E5 can meet this requirement. I am not quite familar with Intel platform. I am wondering if coreboot supports Xeon E5. Thanks. Zheng

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Where do I get cables that can fit a SOIC8 clip?
by Taiidan＠gmx.com 19 Feb '17

19 Feb '17

tl;dr where do I get test clip ribbon cables? no one has cables that small. I already bought another one online that came with a nice ribbon cable (and a nicer mezzanine connection) but I want to make this one functional. rant: I went to a store to get a clip, they didn't have cables for it but I bought it anyone assuming someone I know would have them - they didn't - and then I went back to the store wanting to return it (as it is useless to me), they said that they don't accept returns and the "advice" of the person being the counter was a smug "just solder it" - as if I should rely on a connection that flimsy and easily shortible to connect to many expensive motherboards. In all three EE's total smugly telling me to "just solder it" and none of them having any idea where to get the cables is just bizarre, all that education you think they would understand the importance of doing things properly the first time.

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Re: [coreboot] Libreboot X220 pre-order from Minifree - libre firmware preinstalled
by Taiidan＠gmx.com 19 Feb '17

19 Feb '17

just want to post here what i sent to martin (we cool now) "It wasn't a personal attack, I was simply stating that even after what happened I still liked and respected her more than the purism people - and that If she can figure out how to bypass intels 30 minute shutdown bs that would go a long way to regaining the good will of the community" I can see how my post could have been misconstrued. me_cleaner doesn't make a computer libre and I would think/have thought that leah of all people wouldn't ever end up a snake oil salesman like others are. On 02/17/2017 09:17 PM, Martin Roth wrote: > Please, let's keep things calm and civil. There's no call for personal > attacks of this nature. Let's not create drama. > > Thanks. > Martin > > On Fri, Feb 17, 2017 at 6:24 PM, Taiidan(a)gmx.com <Taiidan(a)gmx.com> wrote: > >> This is a product that doesn't exist yet and that may not ever exist at >> all. >> >> It is dishonest to claim that a computer with ME (nerfed or not) is >> "libre", shame even after all the drama I figured you better than the faux >> libre purism types. >> >> I will be greatly impressed if the 30 minute bullshit is somehow bypassed. >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >>

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Re: [coreboot] Contribution in coding
by Taiidan＠gmx.com 19 Feb '17

19 Feb '17

Hello and welcome!, we are always looking for new acolytes. Feel free to ask any questions you have. I would suggest reading these pages. https://www.coreboot.org/Binary_situation https://www.coreboot.org/Board_freedom_levels To clarify a popular misconception most new users have --- coreboot isn't necessarily libre firmware, or even firmware per say (FSP coreboot is simply a wrapper layer that doesn't do much at all) If you want a *real* coreboot motherboard with native inits: The most popular coreboot mobo is the kgpe-d16, it is the best supported and it doesn't need any binary blobs to work. (but I would get a graphics card because of how crappy the onboard video is) It is a great way to make an affordable gaming PC too (ask me if you want more info, I play the latest games on my KGPE-D16) I would suggest you buy a KGPE-D16 (SSI-EEB) or a KCMA-D8 (ATX) as I am not sure if the below ones work with the current build, but if you want to do development straight from the get-go more affordable boards are the AM1ML (embedded/HTPC) and the H8SCM (mid range workstation), although they are somewhat blobbed unlike the intel (or new AMD) boards there is no DRM preventing someone from remedying this issue.

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coreboot February 2017